Need alternative to 74LVC2G14, with a lot less IDD current in analog mode

A 555 with TRIG+THRESH tied is no more than a glorified '14 with accurate (1/3 and 2/3 VDD) trip points.

I'm reminded of this 555 abuse:

On that note, a good old fashioned comparator is probably of interest. Iq under 1mA, with HC speed, is available.

Tim

That's ridiculous. Maybe Thompson designed it.

Abuse? I can do that.

How would you design a fast schmitt gate that doesn't have shoot-through current near the switch thresholds?

I haven't the faintest idea, but just from the datasheets the performance magnitude is more than 100 to 1 according to which IC is chosen

Or which datasheet is lying? ...Jim Thompson

Use ECL output flip/flop. Fast is relatively easy, but recall that the '555 uses hysteresis for its time delay (aka phase shift) benefit. The only thing fast is the output slew. A flip/flop gives you true and inverting (differential) for free, but you pay ECL prices for the minimal shoot-through.

Smaller-geometry processes could be better than older ones. Or just better design.

But some shoot-through current seems necessary in a gate with hysteresis.

The ECL approach just dissipates a lot of power all the time.

Nope. I don't do hysteresis in gates that way. Besides, I did no "14" style TinyCkt for Motorola/ON ...Jim Thompson

Pretty easy. That is, you can make any shoot through be much faster than the slow input edge would produce in a conventional 6 transistor CMOS Schmitt, and hence, much lower average current.

You use diff pair amps with constant current tails. Sure, it will have DC standby current, but this current can, be made way lower than would otherwise be the case, and academic if the system is always active. Also using resister in the supply's of the final output invertor will lower the shoot through in that stage.

-- Kevin Aylward

Easy, use charge coupled rather than current coupled stages.

It's a simple academic exercise for the student to design such a circuit. ;-)

Tim

The problem isn't the transient current spike when the gate switches; it's the current ramp-up as the input approaches the snap point. All the 74xx14 cmos type parts do that, often several milliamperes against a nanoamp quiescent draw.

Do you know of a way to avoid that, other than just slowing everything down? Diffamps need power. Sure, burning a lot of power all the time hides the shoot-thru issue. Like someone said, do it in ECL.

silly wondering thoughts, why not.... what if each output device were fed by a slight time delay circuit, with each delay being asymmetrical. The idea is that on each transition the on output device turns off slightly earlier than the off output device turns on. FWLIW.

NT

SOP in the H-bridge designs I've done. ...Jim Thompson

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Ahh. I'd only got as far as thinking diodes & pre-existing stray C for the asymmetrical RC filter.

NT

Sounds familiar, but we need names and part numbers.

I can't recall. You'd have to look it up. TI, likely.

This looks like one, Win...

Cheers, James Arthur