Narrow pll loop filter

What do you mean exactly? Is 10Hz a desired close loop noise bandwidth or what?

Looks like the excessive open loop gain, so the poles have to be located at very low frequency.

Avoid the higher order filters in the PLL unless you really need them. It complicates the situation dramatically.

Try dropping the loop gain.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

I want to measure phase noise of generator using low noise VCO tuned by PLL (as described in HP/Agilent Product Note 11729B-1 "Phase Noise Characterization of Microwave Oscillators"). In quadrature, at phase detector output I will see sum of two noises: from VCO and DUT (my generator). But tracking phase loop will suppress phase noise inside loop filter bandwidth, so this filter should be very narrow loop (eg. 10Hz or less). My generator is quite stable, it drifts very slowly, and I think that

It is too complicated for me, I'm not familiar with Laplace transform :-(

It sounds very good, I'll build a simple divider on low noise opamp with 1/10-1/20 gain. At now, VCO gain is about 5e6 Hz/V, D.U.T. works at 80MHz, and Kd is

Thanks,

E.C.

This is a fundamental problem with this sort of PLL. There are two parameters you can vary: the time constant of the zero, and the gain (which sets the pole locations). You can often do something about the gain (by changing the reference and feedback dividers, or the phase detector current), but the zero can be a hard nut to crack.

The time constant (i.e. RC product) associated with the zero will need to be around 5-10ms to get that closed loop bandwidth, for a reasonable damping ratio.

(For at least part of the output spectrum) the output phase noise is determined by the resistor value (from en = sqrt(4kTR) V/sqrt(Hz)), so you want to keep the resistor value as low as you can. Work backwards from your phase noise specification to get the maximum allowable resistor value. If it's 1Mohm, good. If it's 1kohm, you might have problems as the cap gets unreasonably large.

But you also want to avoid large capacitors, as low leakage types get expensive and physically large. Al or Ta caps are cheap, but have leakage current, which might cause a unacceptably large steady state phase error. Hi-K ceramic caps can have microphonics (which may cause hard-to-debug phase noise at the PLL output). Low-K cermic caps are only available up to a few uF or so, and are expensive.

I tend to go for passive loop filters (I'm that kind of guy). In the past, I've used Wima metalised film caps to 1uF. The very last time I designed a PLL (for a SONET clock), I got lazy and just used a 10uF X5R cap that was already in the CAD library. It worked fine.

Regards, Allan

Hi E.C.,

bandwidth

located

Do you mean your VCO gain is 5 MHz / V ? That would be very sensitive. I'd think you'd need a crystal oscillator (or something referenced to a = crystal) for both sources to even think about measuring that close in. But I = could be wrong.

--=20 Regards, Howard snipped-for-privacy@ix.netcom.com