How low? Custom transformers can get pretty weird in form factors. Just remember the 1 Henry coil used in a dial-up modem for wet telco connections, audio coupling transformer that is about as flat as a thick credit card! From memory, 54 Awg wire, no coil form, run multi-amps through to heat the wire so the insulation eases and bonds into its own coil form. [temperature cycling probably kills this thing fast, though.]
spice files are text, simply scoop and post we'll sort out the wordwraps.
Perhaps not. We might be talking about thermosetting (SV) self-bonding wire here - some kind of two-part resin bonding agent where the two components don't react very rapidly at room temperature, but do react quite fast, and irreversibly, when you put enough amps through the coil to get it good and warm.
-- Bill Sloman, Sydney
model for the diode?
in your original post said 50kHz, not 15kHz AND 33uF, not 33nF Glad cause those caps sounded large. I'm assuming all typos and the spice net list is accurate.
not sure how to convert the V1 line, usually V1 n001 n002 description, so does that 5 mean 5Vdc? or AC=5, can't because doesn't appear in the SIN description. The .ac analyses usually don't work well for these types of circuits anyway. looks like I'll throw away that 5.
That netlist pretty much looks like what I did, except I used 33uF and
50kHz, but will work at it a bit.meanwhile change that .tran 100mS to .tran 0 100ms 0 1uS and run it again. I bet you'll find the 'rumbling' goes away. If it doesn't tighten your options for closer/better solution before quitting and calculating the next point.
I set the final time as 1 Second so the minimum frequency would be 1Hz. It's difficult to see 2Hz with only 100mS run time.
.MODEL csd01060 D
...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
In PSpice, I see no wandering, even with no max timestep set...
But there is 18V P-P of ripple before filtering.
For how I quickly checked Mook's circuit, see...
SubcircuitImportByNetlist.pdf
on the Device Models & Subcircuits Page of my website.
Here is his netlist converted to a subcircuit...
***** Mook Johnson Voltage Multiplier ****** ******* IN Viewing Nodes ******* | | | | .SUBCKT MOOK_Multiplier V1_P C21_N R6_N D1_N *#SIMETRIX C10 C10_P C8_P 33n C11 D6_N D5_N 33n C12 C12_P C10_P 33n C13 D7_N D6_N 33n C14 C14_P C12_P 33n R1 R6_N C21_P 5k C15 D8_N D7_N 33n R2 R6_N 0 20Meg C16 C16_P C14_P 33n R3 0 C21_N 50k C17 D9_N D8_N 33n D10 C1_P D10_N CSD01060 C39 R6_N 0 1n C18 C18_P C16_P 33n R6 D1_N R6_N 1Meg C19 D1_N D9_N 33n D11 D10_N C2_P CSD01060 D12 D2_N C4_P CSD01060 D1 C18_P D1_N CSD01060 D13 D3_N C6_P CSD01060 D14 D4_N C8_P CSD01060 D2 C2_P D2_N CSD01060 D15 D5_N C10_P CSD01060 D3 C4_P D3_N CSD01060 D16 D6_N C12_P CSD01060 D4 C6_P D4_N CSD01060 D17 D7_N C14_P CSD01060 D5 C8_P D5_N CSD01060 D18 D8_N C16_P CSD01060 D6 C10_P D6_N CSD01060 D19 D9_N C18_P CSD01060 D7 C12_P D7_N CSD01060 D8 C14_P D8_N CSD01060 D9 C16_P D9_N CSD01060 C20 D10_N 0 33n C21 C21_P C21_N 1n D20 0 C1_P CSD01060 C1 C1_P V1_P 33n C2 C2_P C1_P 33n C3 D2_N D10_N 33n C4 C4_P C2_P 33n C5 D3_N D2_N 33n C6 C6_P C4_P 33n C7 D4_N D3_N 33n C8 C8_P C6_P 33n C9 D5_N D4_N 33n .MODEL CSD01060 D
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
I posted a correction. The "rumble" is similar be it 15K or 50KHz. I was just playing with the values to see if it would go away. it doesn't. I did the 1uS thing and it did get substantially reduced. like you said maybe a simulation thing.
I'm just wondering of it is the diode biasing thing is why I'm seeing similar results with the lab setup. these have high Vf and if not all are biased on at the same time thats 20-30V of Vf that can modulate the output voltage. As an experiment I may try to load each tap to see if the output stabilizes.
THANKS!!!
Also, I found the problem with the apparent instability! at least think I have.
I let LTspice run on its own [only specifying STOP time] and had some wobbling, but less than 0.1Vrms, not that 2V reported.
THEN I forced the steps smaller, down to 5uS max [which as you and I both know is the only way to sometimes smooth down a .tran analysis] and then I actually got more than 2V wobbly!! say what?! upon inspection of the plot, found that the plot program itself decimates the data, making it really 'chunky' looking, ramps between data points were NOT 5uS, but rather anywhere from 50uS to 65uS and all over the place! Ran the EXACT same analysis again, but this time used .options plotwinsize=0 to prevent the plot program from chewing up the data and VOILA! the wobble dropped below 1uV !!! in the FFT, below -90dBV
So there are two-fold places to look when you see unstable answers. First place is to ask, "Are my maximum step sizes small enough?" and the second place is, "Does the plot program chew up my very smooth data?"
In this case, it was the plot routine chewing up the data and therefore injecting noise into the results!
I'm tempted to apply .tranoise just to see what happens in a more accurate siimulation.
But that will take over 42 independent noise sources [2 each for diodes and one each for source and load resistors], but would be fun to see the results.
42 is THE answer Mark
LOL!
Yes.
remodel the diode with high cap and a 1 meg R around each one and then run the sim again.
Jamie
you must have missed my reply to Jim Thompson posting the model for the CSD diode
=-=-= Also, I found the problem with the apparent instability! at least think I have.
I let LTspice run on its own [only specifying STOP time] and had some wobbling, but less than 0.1Vrms, not that 2V reported.
THEN I forced the steps smaller, down to 5uS max [which as you and I both know is the only way to sometimes smooth down a .tran analysis] and then I actually got more than 2V wobbly!! say what?! upon inspection of the plot, found that the plot program itself decimates the data, making it really 'chunky' looking, ramps between data points were NOT 5uS, but rather anywhere from 50uS to 65uS and all over the place! Ran the EXACT same analysis again, but this time used .options plotwinsize=0 to prevent the plot program from chewing up the data and VOILA! the wobble dropped below 1uV !!! in the FFT, below -90dBV
So there are two-fold places to look when you see unstable answers. First place is to ask, "Are my maximum step sizes small enough?" and the second place is, "Does the plot program chew up my very smooth data?"
In this case, it was the plot routine chewing up the data and therefore injecting noise into the results!
I'm tempted to apply .tranoise just to see what happens in a more accurate siimulation.
But that will take over 42 independent noise sources [2 each for diodes and one each for source and load resistors], but would be fun to see the results.
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