Limiter + Opamp + Reverse phase on negative swing

Yes, it is a common feature. Typically, only amps which specifically = note "no output reversal" are safe from this.

Single supply amps (including LM358, comparators like LM393, etc.) are = prone to this, a small sacrifice for getting inputs down to -0.3V.

Cue larkin to talk about his new favorite FET current limiters. :)

Tim

--=20 Deep Friar: a very philosophical monk. Website:

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output reversal" are safe from this.

this, a small sacrifice for getting inputs down to -0.3V.

LM324/339 types can be even worse. Pull one pin of one opamp a few tenths below ground, and all the opamps on the chip go nuts. You can also sometimes observe a *double* phase reversal as you go negative on an input pin.

Real men use polyfuses and transzorbs.

John

output reversal" are safe from this.

to this, a small sacrifice for getting inputs down to -0.3V.

One protection scheme...

dates back 9 years, in answer to an original post by Spehro. ...Jim Thompson

Consider the case of the 'inv input' being between -v and +v and higher than the 'non-inv input'. The output will go low as expected. Keep raising 'inv input' and it will eventually force the output to an incorrect high level. It gets worse if 'non-inv input' is driven too high - the output will be an open circuit that may receive current from outside the pair.

What's worse is that the pins and parts inside most linear ICs are isolated from the substrate by back-biased diode junctions. Pull a pin a little below V-, and you forward bias these diodes. In lots of chips, that will spray charge all over the place and mess up all sorts of stuff. Worse, some chips will find a sneak SCR somewhere in their layers and latch up. LM34, for example, is a superbly sensitive latching spike detector. The original 4000 series digital CMOS parts ditto.

It's impressive how many IC designers ignore both of these effects, by accident or on purpose.

John

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I take great umbrage (er whatever that means ;-) ) that latchup is ignored by designers. Parts need to pass some corporate latchup limit else they are not allowed to be sold. The limits are not so great for analog chips, but most companies insist on 40ma or so at room temperature. Prior to tape out, the layout is studied for potential latchup situations and false collectors are added to the design where needed. Standard input protection should have the false collectors in their layout.

"Doctor, it hurts when I pull pins beyond the power supply rails." "Well, don't do that!"

On purpose? Come on John, get real. ...Jim Thompson

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How I wish those rules had the force of law. Latch up a chip, go to jail.

Tell that to Spike.

John

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For CMOS, you could do a little footwork and find the manufacturers using an epi process. Nothing helps bad latchup layout like epi. I really don't know anyone on bulk CMOS these days, but I hardly see the entire market.

You have to realize if a part is latchup prone, it is a pain in the arse for the manufacturer too. The parts need to pass a burn-in, and if the burn-in is dynamic, latchup will get ya. Then they have to insure the part doesn't latchup under test. Really, I can't see very latch up sensitive parts being sold in volume. This is especially true with off-shore testing, which turns small problems into big problems due to time and language differences.

Do you have a license for that rubber chicken?

I only laugh when "miso" hurts ;-) ...Jim Thompson

-- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

I always wanted to know what they feed rubber chickens...