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The LT1722 is a $1 bargain:

Version 4 SHEET 1 2108 772 WIRE -448 -592 -528 -592 WIRE -288 -592 -368 -592 WIRE -208 -592 -288 -592 WIRE -16 -592 -128 -592 WIRE -288 -528 -288 -592 WIRE -1248 -512 -1248 -560 WIRE -1088 -512 -1088 -544 WIRE -1248 -416 -1248 -432 WIRE -1088 -416 -1088 -432 WIRE -288 -416 -288 -448 WIRE -288 -320 -288 -352 WIRE -1360 -304 -1408 -304 WIRE -1232 -304 -1280 -304 WIRE -1120 -304 -1152 -304 WIRE -1008 -304 -1056 -304 WIRE -832 -304 -928 -304 WIRE -656 -304 -784 -304 WIRE -288 -240 -288 -256 WIRE -640 -224 -784 -224 WIRE -528 -224 -528 -592 WIRE -528 -224 -560 -224 WIRE -320 -224 -528 -224 WIRE -304 -224 -320 -224 WIRE -1408 -208 -1408 -304 WIRE -16 -208 -16 -592 WIRE -16 -208 -256 -208 WIRE 48 -208 -16 -208 WIRE -320 -192 -368 -192 WIRE -304 -192 -320 -192 WIRE -288 -144 -288 -176 WIRE -832 -128 -832 -224 WIRE -656 -128 -656 -304 WIRE -368 -128 -368 -192 WIRE -1408 -80 -1408 -128 FLAG -1088 -416 0 FLAG -1088 -544 +V FLAG -1248 -416 0 FLAG -1248 -560 -V FLAG -368 -128 0 FLAG -288 -144 -V FLAG -288 -256 +V FLAG -656 -128 0 FLAG -288 -320 0 FLAG -832 -128 0 FLAG -1408 -80 0 FLAG 48 -208 OUT IOPIN 48 -208 Out SYMBOL voltage -1088 -528 R0 SYMATTR InstName V1 SYMATTR Value 5 SYMBOL voltage -1248 -528 R0 SYMATTR InstName V2 SYMATTR Value -5 SYMBOL ind2 -768 -208 R180 WINDOW 0 -4 79 Right 2 WINDOW 3 -2 41 Right 2 SYMATTR InstName L2 SYMATTR Value 2m SYMATTR Type ind SYMBOL ind2 -848 -208 M180 WINDOW 0 -4 79 Right 2 WINDOW 3 -2 41 Right 2 SYMATTR InstName L1 SYMATTR Value 2m SYMATTR Type ind SYMBOL res -352 -608 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 47 SYMBOL res -112 -608 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 47 SYMBOL res -304 -544 R0 SYMATTR InstName R4 SYMATTR Value 39 SYMBOL polcap -304 -416 R0 SYMATTR InstName C2

SYMATTR Description Capacitor SYMATTR Type cap SYMATTR SpiceLine V=63 Irms=800m Rser=0.081 Lser=0 mfg="Nichicon" pn="UPR1J471MRH" type="Al electrolytic" SYMBOL polcap -1120 -288 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C1

SYMATTR Description Capacitor SYMATTR Type cap SYMATTR SpiceLine V=63 Irms=750m Rser=0.16 Lser=0 mfg="Nichicon" pn="UPG1J221MRH" type="Al electrolytic" SYMBOL Opamps\\LT1723 -288 -272 R0 SYMATTR InstName U3 SYMBOL ind -544 -240 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L2_LEAK

SYMBOL ind -912 -320 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L1_LEAK

SYMBOL res -1264 -320 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Z_SOURCE SYMATTR Value 75 SYMBOL res -1136 -320 R90 WINDOW 0 -5 59 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 75 SYMBOL voltage -1408 -224 R0 WINDOW 123 24 44 Left 2 WINDOW 39 0 0 Left 0 SYMATTR Value2 AC 1 SYMATTR InstName V3 SYMATTR Value "" TEXT -832 -392 Left 2 !K1 L1 L2 1 TEXT -1032 -472 Left 2 !.ac oct 10 10 100Meg TEXT -872 -360 Left 2 ;Murata DA102JC

Reply to
bitrex
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Or, showing the isolation:

Reply to
bitrex

This isn't the right way to represent a real transformer in LTSpice. Leave out the 0.5uH leakage inductors and just write K L1 L2 0.99975 - which is probably unrealistically optimistic.

--
Bill Sloman, Sydney
Reply to
Bill Sloman

Bode plot looks about the same. Performance of the actual circuit on a sheet of copper-clad is very similar to the sim, the ~1dB peak at about

8.5 MHz is there and the low-frequency -3dB point is a bit higher, about 50Hz.
Reply to
bitrex

DC resistance of the transformer is about 0.5 ohm

Reply to
bitrex

ave out the 0.5uH leakage inductors and just write K L1 L2 0.99975 - which is probably unrealistically optimistic.

What sort of parallel capacitance have you plugged in for L1 and L2? You m ight need to include a third inductor with a resistive load to represent th e current induced in the transformer core. With a nickel-zinc ferrite core the resistance would be fairly high. TDK has got data sheets

formatting link
/ferrite_summary_en.pdf

but it won't come up for me now - if memory serves its a fairly voluminous file.

--
Bill Sloman, Sydney
Reply to
Bill Sloman

Will that work in real life? The DC gain is huge.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

I think you are accounting for the leakage inductance twice.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

Yeah it looks to work quite nice on the copper-clad, the low-end bandwidth is phenomenal for such a small transformer, the current-feed topology helps a lot.

It's variation on a circuit from an app note on the topology, can't find it now but I think it may have been Renesas? The idea is to use a transformer with decent low-frequency response but relatively large leakage L, leverage the high open-loop gain at low frequency to extend the bandwidth there, but loading on the op amp output increases the primary-side leakage L as seen by the op amp input, so there's peaking added to boost the high freq gain back up.

Performance on the board is pretty similar to the sim. The 1722 is a very well-behaved for a 200MHz/70 V/usec amp, they claim this in the datasheet and it seems true, on copper clad at least in this arrangement it doesn't seem prone to instability at all.

The peaking might not even be needed it has 50 mA drive current, typical and a full-power bandwidth at 1V peak of 9MHz

Reply to
bitrex

Hard to find good intel on what an appropriate low-frequency cutoff point for an NTSC composite signal is, exactly. What component extends down to 60 Hz, like the envelope of the vertical sync-pulse train?

Reply to
bitrex

If you effectively short the transformer secondary, LF response goes way down below data sheet values, to w=Ls/Rs or something.

The DCR of that transformer isn't specified. The DC gain of that circuit could be huge, and make a lot of offset at the output.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

Here's some scope shots from the Rigol, input is 1V P2P sine using 50 ohm source and 50 ohm terminator but all other values the same, DC coupled, acquisition set at 128x averaging:

5MHz:

500 Hz:

90Hz:

Saturation distortion becoming un-rectifiable below about 100 Hz

Reply to
bitrex

For parallel C, nothing at the moment. Too simple a circuit to spend much time futzing with in simulation, just went straight to the breadboard and rigged it up to test with the values as indicated. The performance of the real circuit is pretty good, whatever the particulars of this transformer are.

Reply to
bitrex

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