Intel Processor System Management Mode Question

Hopefully, someone in this group is knowledgeable on this subject as I cannot seem to find a decent forum. Anyone with a forum suggestion would be appreciated.

Anyway: I've been studying internet material (including a few Intel specs) regarding the nuts-n-bolts of 'system management mode'. I've discovered a handful of contradictions that leave me confused.

When entering SMM, does the processor change to Real Mode regardless of whether the application was running in protected or real mode at the time of the SMI interrupt? I've seen references where this is confusing as one reference mentions that after entering SMM, you cannot write to the CS segment register if you were originally in protected mode. This I understand but the way I thought I understood the technique, was that when in SMM, your in RM (actually Large RM or Flat Mode. In that case it *is* ok to write to the CS register.

I've seen the Intel reference mention the CS as a 'selector' upon entering SMM. I understand this to mean that the CS contains a GDT/LDT table offset. However, their example shows the CS being initialized (upon SMM) to a the base address segment, not a selector. Just trying to clarify what is going on.

If anyone understands what I am asking, I could sure use some guidance. Thanks Jim

Reply to
Jim Flanagan
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I guess your doing an embedded project. I would try the Intel Embedded Community forums as they would most likely have the answer.

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Cheers

Reply to
Martin Riddle

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