I'm popping MOSFETS....linear derating factor involved?

So if all the opamps rail, fet differences again dominate, and one fet could be doing most of the work.

John

Whoa, never heard about those type of problems, thanks for the info.

I will be double-checking for oscillations as it's becoming clear to my bull-headed brain that I can't assume just because I didn't see oscillations early on that they aren't there.

If the wiring inductance is causing excessive gate voltage (and for conversation's sake the inductance can't be reduced), would would be the best way to stop that? Slow down the gate further, use the previously recommnended ferrite beads, place TVS or zener's on the gate?

Yea, measuring those temps is tricky....hate it.

I'm fairly confident of my case temperature measurements though as I compared thermocouple readings taken from the "notches" in the sides of the TO-247 case (where the metal thermal pad is exposed) to readings I took when I drilled out the heat sink behind the thermal pad. They were within 2 degrees-C of each other. I'm using the "notch" temp measurements now....much easier to take.

Yea, may have to go that route. No room though for the supporting circuitry though. There's always something! :-)

I think this might be critical. I was hoping to use 5V because of some other circuitry that needed to be added but when it was mentioned earlier (I've forgotten who) I realized that this could be a big gate voltage problem. Vcc is now

Now I just need to wait for the new shipment of FETs (arriving tomorrow) as I've blown all of mine up. :-)

Thanks Win! John

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It's funny how obvious a problem this is now....never saw it. :-)

I haven't measured the gate voltage at the full 15A load but at about

If I had any more FETs left I'd just hook them up....I gotta' wait 24 hours. :-)

John

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OK, here's another monkey wrench - copper heat spreaders. :-)

Good Luck! Rich

Ws not W/s but yes.

yep.

voila.

it assumes there are none, and that the heat is evenly distributed throughout the mass. its quite valid for the die, but less so for the heatsink. but you can do a crude thermal resistance calculation to guesstimate the drop across the heatsink. Or take spreading into account and do a more accurate calc.

most heatsinks comprise a large mass and some fins. ignore the fins and this technique is reasonably valid. measure the temp at either side of the fat bit, they wont be too far apart - as a crude Rtheta calc ought to show.

Cheers Terry

You're a cruel man Rich. :-) I actually have a few pieces of 1/8" thick Alloy 110 copper I was going to test to see if it made enough of a difference to be worth it. I'm a bit worried about getting the surface flat/smooth enough to really sit well against the heat sink though. Commercially available plate/sheet material has a lot of scratches, etc., and I don't want to have to machine new surfaces onto these.

I'm definitely testing them though, as soon as I can stop popping FETs!

John

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Most fet data sheets post a *typical* transfer curve. But it will vary a lot from part to part, and with temperature and drain volts.

It's like Mother Nature spends all her waking hours scheming to find subtle bugs to plant in our hardware and software, and makes sure they are disguised or tangled with other bugs, so that they're hard to find.

John

Actually, that calculated temp rise being for the die works better for me. I'm only really concerned about calculating the junction temperature when the sink is warming up as I can easily measure the sink temperature in a couple of places if I need to (for optimizing FET placement, showing whether a heat spreader is working well enough, etc.).

Thanks again Terry, John

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I took a look at the LT1013 specs again and I believe the output can only go to 4.0V-4.4V (60ohm load to no load) with a Vcc of 5V. Assuming 4.0V max output, I checked the IRFP2907's transfer curves.

I had to extrapolate down to a Vgs of 4.0V but at 15A it appears that I am wayyyyy to close to the drain-source current rating, even at a Tj of 175C.

If I assume that the junction temp is cool (like when the load is first turned on and I always seem to blow my FETs, in a few seconds), the FET is only rated for 9A when I'm trying to push 15A thru it. This is a problem!!!

I'm definitely going back to a Vcc of 9V. And I'm soooo pissed off at myself. I KNEW this about the FET and lower Vcc voltages for the op-amp affecting my max gate voltage. I completely forgot about it for these latest tests. Ten expensive FETs later, and with everyone's help, I'm finally beginning to see the light again.

Of course, I could still be oscillating too. :-)

Amen brother.

John

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The thermal conductivity of the heatsink material being that much greater than conductivity to the air or of the air, the convection contribution to cooling can be ignored over short time periods for a step change in power, starting from the zero power or quiescent power condition.

The method is usefull more for calculating power loss, particularly on heatsink structures that depend on forced air. Removing the air flow allows the sink to assume a relatively uniform temperature throughout. If I see a temperature gradient across the heatsink of greater than ten degrees, I'd be doubtfull of the suitability of the technique in the specific application.

The record of changing temperature will show if you're able to make the first order approximation - so long as it's a relatively straight line (deltaTemp/deltatime), it's still responding linearly to the impulse.

In your case you know the power level and were only interested in what local variations would result from short-term changes.

RL

Nicely put. most of the thermal profiles I have looked at end up with first-order step responses. Its a whole different story with time varying loads of course.

A few years back I wrote a little mathcad worksheet to do a first-order exponential curve fit from measured data. it ended up being automagic, add another reading and it re-does the curve fit. I also calculated R-squared, which is a measure of goodness.

that way I could do a whole bunch of otherwise lengthy thermal tests, and wait no more than 1 time constant. I did several calibration runs, and it worked pretty well. IIRC by about 0.5 time constants R^2 > 0.95.

bloody handy when a thermal test takes 8 hours, but you can get results in 30 minutes, and within 10% of T_ss by 1hr.

Cheers Terry

Sounds interesting, since im also working at a highish-power active load.My specs so far are 50v/50A/350w (with at least 40A at 1v being possible).Cooling via 150mm long fisher electronic SK06 (.5k/w) with 2

I was planning to use 6 IRFP260N, each with its own control loop. Now reading that high voltage (the 200v 260N is "high voltage?) FETs can be problematic, im worried that i have to begin everything from scratch again. I built a smaller active load some year back with a 300v 350N and it was stable (at least it looked so on my only scope back then, 10Mhz, now theres a 50Mhz analog and a 20Mhz DSO) and it didnt blow yet, so maybe it could work?

So what are your words on this, can it work or should i use something else instead? The 260N were promising because of their good Rth j-c /price ratio and low enough Rds and high voltage margin for spikes of any origin.

Looks interesting, for the fact of using only one OP per FET. My old plan involved 2 OPs each so thats much better (my control card has to fit in the case vertically and the old one doesnt really do) Now i seem to have a (hopefully) temproary brain blockage caused by a math test i wrote today and dont really understand how it works, so some hints might be good. My app calls for 10A/FET at 5v control voltage (from a DAC), supply +-15v.

-- Robert

An update....

After receiving a bunch of shiny new MOSFETs, I decided to restart the tests with a few of the recommended circuit changes:

- Shortened the leads as much as possible to reduce inductance.

- Used ferrite beads on all leads (I had a bunch and for the prototype I decided to spread them around).

- Beefed up the lead connecting the GNDs for the two power supplies (one for the FETs and one for the op-amp and passives).

- Raised the op-amps Vcc to 12V to increase the MOSFET gate voltage, when necessary.

After a bunch of successful intitial tests, it looks to be working well. Heat sink temp is 86C, which is approximately a junction temperature of 158C (based on theta_jc and theta_cs for the FET) for the 125W load for each FET. This is plenty darn hot for the tests and as far as I want to go (rated max is 175C for these FETs).

I'm in the 2nd hour of a thermal cycling test which brings the FETs up to a heat sink temperature of 83C and back down to 30C every four minutes. I believe that this is more strenuous than merely holding the FET at a high temperature, though I did that for a couple of hours first.

But, something interesting happened which might explain some of my popping FETs.... I happened to have the scope hooked up to the gate of one of the FETs when I turned off my 12V halogen desk lamp. The gate voltage jumped to 10V (from 3.6V) for 100uS or so!! A turn-off spike from the transformer in the power supply for the lamp? This resulted in a 25A surge thru the FET (max. for the power supply, at 27V or so) and might explain why my FETs were popping when not expected. The SOA graph for the FET says it can take 400A at 27V for 100usec but what happened can't be good for the FET. Maybe it weakened the FETs? I've turn that lamp off several times during earlier tests. Most likely I had oscillation problems too though.

After a couple of days of thermal cycling, I'll start the heat sink temp rise vs. time plotting and see how much power these puppies can handle while warming up and for how long.

I'll post the results of all the tests when I have them. Thank you everyone for all the help and suggestions! The FET-popping problem seems to be gone (famous last words?), hopefully the testing confirms that.

John

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That's assuming the junction starts at 25C, you have to massively derate the value otherwise.

There's the spec called "SOA" that you should heed.

Look at the cute graphs in the back of the spec sheet. Look closely. You'll see the FET can take the listed XXX amps and YYY volts, but not at the same time. Used car specmanship at its best.

Also if you want reliability, consider using a safety factor of TWO or better for your max dissipation, SOA, and voltage and current limits. There's a reason mil-spec equipment derates components! The stuff lasts a heck of a lot longer.

If you really need a big SOA, consider switching to using IGBT's, which have much much wider SOA envelopes, like 98% of E and I in many cases.

Amazingly, the Max SOA graph in the datasheet for the IRFP2907 has the junction temp at 175C. Of course, they have the case at 25C.

Since my case temp is a lot higher, but with a junction temperature lower than 175C, would I still need to drastically derate SOA for the FET? Not that I would be able to figure that out though. :-)

John

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LOL, they sure don't make it easy to figure things out. :-) I wish that IR had a DC SOA instead of just the pulse plots. They only go up to 10mSec pulses, nothing longer.

I agree. It's become more of an interesting experiment in what I can get away with for this one. Especially since it's the first time I've popped FETs without bumping into something or letting the DMM or scope probe slip.

Don't really know anything about them. Are they as easy to drive linearly (not hard on/off) as MOSFETs?

John

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Sure, although they're almost never used in the linear range (though it does look very linear as such!). There are a few DIY audio amps, not class D, using them, around the internet.

Dunno about oscillation. Supposedly you can drive the gate harder (e.g., turn-off diodes and such), which means less series resistance which means less or no series "stopper" resistor (or possibly ferrite bead).

There's also the matter of the internal PNPN junction that looks scarily like an SCR, and what concerns me is that appnotes tend to glaze over it, saying "oh well as long as current stays below this coefficient then it's fine", just a little vague eh? Under fault conditions, 20V or so gate drive is certainly enough to force a couple hundred peak amps. Current sinking is no problem for these things, so what is latch current?

Latching should of course be no problem for you, since you've got current sense. I don't know if avalanche characteristics (apparently essentially nonexistent!) will be a problem, but you've already noted possible problems with transients.

Oh, and they're usually a bit cheaper and more efficient than MOSFETs of the same voltage, power and conductivity, but they also saturate with more voltage (a solid 2-3V across 1-200 amps, compared to a roughly ohmic characteristic allowing milivolt saturation in some situations for MOSFETs). Wonderful for switching 300V and up, but MOS rules at low volts.

Hmm, and it seems to be 4:20pm.

Tim

-- Deep Fryer: a very philosophical monk. Website:

That's not unreasonable. In switching apps, and even most of linear apps, you don't see the max voltage and the max current at the same time.

DC SOA is just the thermal resistance and max junction temp stuff. It's all a matter of power. The only exceptions to a pure power curve is the max voltage (breakdown) and max current (wirebond) limits.

One of the IR datasheets has some dpak fets that the datasheet proclaims, in big type, are rated for 110 amps or something insane like that. Then there's a tiny footnote somewhere on page 19 that says they're actually "package limited" to 70 amps, meaning they would do the 110 except for the wire bonds.

John