I am looking at interfacing an ADS 8344 Ti ADC chip to a Bone. The ADC is controlled serially through a single control pin. Can anyone tell me how to program such a sequence from a Beagle Bone or other mcu? The sequence is coded as 24 high signals to select 1/8 channels and receive the 16 bit answer. How is synch maintained? A shift register? thanks for any help. curious, jb
Don't know about the Bone but it looks a lot like a SPI port. You might be able to hack that. Don't know if bit-banging will work but it might with the internal clock.
OK Thanks for the pointer. So I guess the next question is how to program SPI. Luckily, there are tutorials on this:
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One problem ("issue" for you liberals :) is that SPI is a "de facto" standard, and can vary in details across various hardware platforms. But the above tutorial is done in Python, and used an LCD screen with SPI to experiment on.
Now what about storage of results from the ADS 8344? Let's see - 8 channels at
100 khz, 16 bit data size = 200 kBytes/s x 8 ch = 1.6 MBytes/s. Since USB 2.0 can do 20 MBytes/s (realistically in the noise dog pound.), then in theory the Bone can store results as they come in.
May I have a stylized rant against the inefficiencies that drag us down like Besenjis against lions? It is this: These SBC's need a fast IO bus like SATA 3 or USB 3.0 to take advantage of SSD-type drives on storage, as well as data input devices. Perhaps there is a hardware barrier to doing this, but a feral reptile brain part of me suspects that the hardware companies are "dumbing down" the boards the way IBM tried with the 5 mHz (!) PC AT.
In designing a SBC, why be a follower to the compromises of the PC? In any case, ISTM the hardware for SATA 3 and USB 3 has been developed already, so what's the problem with adding them to a SBC? The payoff is tremendous.
On Sat, 10 May 2014 10:31:28 -0700, John Larkin Gave us:
You do not make rules. You compromise and sully the character of intelligent men everywhere you get a chance to do so. Pretty characterless, honorless, and pathetic.
It is your responsibility to make it work. Generally that means actually understanding what's going on, not blindly following the example of someone making a lot of noise.
Fortunately SPI only comes in a few flavors, so if you're lucky the low- level parts of the code will Just Work.
If it can't, then consider using that same SPI bus to talk to a memory card or memory chip. Just sweep aside all of the stuff on the board that makes it easy to talk to the OS and all, and speak directly to hardware through the SPI port.
Why be a follower to the compromises of a PC? Do you like the price of your Beagle Board? Do you like the fact that you didn't have to design it? Then why are you complaining?
It's easy enough to design circuits yourself. One of my former clients makes some exceedingly cool stuff. He's a former carpenter, and has exactly the same amount of formal education in electronics as any other carpenter out there. Yet, through enthusiasm, deep study of data sheets and web sites, and hard work, he's the chief EE for his company and makes circuits which are every bit as professional as people that I've worked with in industry.
(Of course, he's smarter than average -- why else would he have hired me to help him fill in the gaps in his knowledge when he had some heavy duty analog circuits to build?)
--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
Wow - speak directly to memory? Actually, the mini-itx board, the Asrock, has a SATA 3 and USB 3.0. SO what I am looking for is a way to interface a ADC chip in via a SPI serial connection. Any ideas? (It would require a SPI-type interface...a pci card with that?) jb
For a little while, that might eventually gag both the ram buffers and SD card.
like
SATA 3
data
feral
"dumbing
SO you weren't there. Memory speed was a difficult problem back then with
180 ns access times and 380 ns cycle times for DRAM. Unless you really paid a lot for faster stuff. There was little point in trying to run the processor faster than memory could provide instructions and data.
any
so
The scaled memory speed issue as seen back in the AT days.
In addition, the original IBM PC used the 8088 processor with only 8 bit data bus, no cache and a primitive instruction set.
A minicomputer a few years earlier had core memory with about 1000 ns cycle time, but the memory width was at least 16 bits, some small 64 to 256 bytes/words (not kilobytes) cache and often a much more expressive instruction set and the performance was very much better.
Well, I wouldn't call it primitive. 6800 / 6502 was primitive. 8080, Z80, etc. not too bad; handy, but low powered, and definitely simpler than the 8086 or 68k.
8088 and 8086 competed against the 68k, after all. Probably, RISC series cores didn't approach the same complexity as them until, say, ARM or so (which wasn't really that far off after their introduction, anyway).
Compare IBM PC, somewhere in the XT to AT days, to the various "boxy" Apple Macintosh models.
Ironic that the 8088 took the exact opposite tack from the 68k. More bits? Pffbt, less bits! We don't need no steenkin' memory anyway! :)
And just to make things absolutely horrible, they also made the PCjr, with an 8088, and video RAM for system RAM...
"Expressive" mainly meaning (from what I understand of, say, PDP architectures...which isn't much), the instruction set was easily as rich, but actually orthogonal, so you didn't have to remember every damned rule and exception, it just worked. And often, chaining operands (pointer arithmetic and indirection?) 'til the electric cows come home. Who needs compilers!
I'm curious, what exactly do you need SATA for? What is the sample rate of your ADC? How many bits? Are you sure you can't shove the data onto an SD card? They run pretty fast and are a lot easier to use than an Asrock, OS, etc, etc, etc.
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