High fashion crystal oscillator?

I've given up trying to decipher vendor pricing. For example, this relay

But you can get the whole DIN-rail carrier AND the relay for only $10.05

And this wasn't really the example I was trying to find. There's another model (same family) where it is much cheaper to purchase the DIN-rail version (complete with relay), than to buy the relay itself!!

Well, yeah, all the usual stuff, but not really of much note to precision xtal oscillator applications.

Its all about stability of oscillator frequency verses temperature, supply and load and phase noise.

Many applications like quite a tight 50:50 duty cycle though. xtal oscillators automatically give not a bad sine wave to drive the limiter/squarer.

The limiter is always the dominant flatband noise source.

I agree, the key to most really high performance designs, is not the so much the design, as the process.

What's your point?

Its what they claim in their data sheet.

My take is that this topology's apparent success is down to having maybe,

It is very common for people to not understand how a topology really works and attribute all sorts of nonsense to it.

A typically one is here:

-- Kevin Aylward

Since nobody seems to have tried it, it is still an open question.

If you could be a bit pickier about how you sustained the oscillation, you might at least be able to take the supply sensitivity out of the game.

Crystal oscillators tend to have remarkably high Q-values, so the sustaining current fed into them doesn't get the chance to generate much non-sinusoidal voltage across the crystal.

But if you controlled the sustaining current more carefully you wouldn't need a limiter.

They seem to have been able to come up with unexpected solutions. There weren't many people in the area who could do that - I can't think of any others - but those two did exist.

Data sheets do seem to be influenced by what the marketing people want to be said. They can't mess around with the performance claimed, but everything else seems to be open to spin.

Seems reasonable.

Since nobody seems to have tried it, it is still an open question.

The supply sensitivity is taken out because I have a 100dB psrr on the regulator. It is truly the easiest way to do it. 50 transistors in a regulator, is nothing.

Its absolute impossible to design the oscillator itself with the required ps rejection. The oscillator is optimised for noise. 10,000 transistor are used to temp comp and linearize it. Its the ONLY way to do it in practice, at high performance levels.

Well, sure....

This is not the limiting of the oscillator, it is the squaring up

..and your knowledge of my own professional career solutions to problems is what?

What I can say, as an example...

Lets take the absolute best low noise (BG) regulator from Analog devices.

For example the LTC6655. It needs 5mA standby current. It shows a flatband noise level of 50nV/rthz

The BG regulator in my oscillators use 100uA (or less) to achieve that noise.

Now, noise goes with the sqrt of the current. Using the Widlar et al techniques would mean that, all things being equal, that my design should result in (5/0.1)^2 = 2,500 times more noise. As far as I can see from looking at the mainstream venders, none come remotely close to the noise/current ratios achieved in my regulators.

The reality is, things have moved on. Many techniques the old guys used, whilst very clever and appropriate at the time, have little relevance to today. Way more sophisticated techniques are required.

The oscillators ASICs I design might target a total of only a few mA total supply current, yet they still need < 50nV/sqrt noise performance for their regulators. Legacy elementary designs just don't cut it. Today 10,000s of transistor cost, essentially, nothing.

Today, its computers running 10,000 faster for simulations, with the availability of 10,000s of transistors at < 1 cent cost. Producing "clever"

-- Kevin Aylward

on

ou

Bob Widlar did the same thing in his version of NE555 - the LM122 - albeit with a much slower timer. Sadly, it never sold well and is now obsolete.

ps

sed

The only one that anybody has come up with so far.

The problem there is presumably the uncertainty of the position of the edge s of the square wave - a comparator is just a fast amplifier, and amplifier s have input noise which make the edge detection happen earlier or later th an it ideally should.

What you need is Percival distributed edge detector, where half a dozen sep arate comparators look at progressively delayed version of the same edge, a nd add the delayed outputs together after further complementary delays. Six of them would only give root six (2.45) reduction in the noise, but that m ight be worth having - if you have 10,000 transistors to play with, a littl e redundancy is permissible.

Similar things have been done in similar contexts.

You seem to be confident that you are onto something, but don't seem to be able to find the words that make the idea intelligible.

the

of

is

You don't boast about the patents that name you as an inventor, for starter s.

Bob Widlar and Barry Gilbert didn't have to - their names kept coming up in patent searches.

I spent a couple of years at EMI Central Research and got two patents out o f it - places like than (and IBM) patented pretty much everything they coul d (even krw has got a couple patents out of his IBM time) but I did get exp osed to people who were seriously creative.

Am 05.01.19 um 13:32 schrieb Kevin Aylward:

No, if you can burn some power or do it not in a simplistic way.

That is not exactly big news.

Oliver Collins: The design of low jitter hard limiters <

(I have seen it outside of the IEEE Wall Of Shame in the wilderness of the internet.)

And the LTC6957 family is also not bad.

Don't make me laugh so hard. The LT6655 is a bandgap reference that is quite good as far as bandgaps go noisewise. 50 nV/rtHz is about a careless implemented LM317.

A low noise voltage regulator is the LT3042/45, featuring 2 nV/rtHz. (And finally, there is the negative Version also, LT3094)

Just like the LT3042's reference current source. The rest is only a follower.

I have no doubt that Widlar could still point his index finger.

Unfortunately, he has died nearly thirty years ago. Not exactly fair to to target him for a comparison.

regards, Gerhard

Bandgaps are about 20 dB noisier than buried zeners, because they have to multiply delta-Vbe by a factor of 10 and then add it to Vbe to get the TCs to cancel.

And of course if you have some reasonable load like 500 uA, a cap multiplier with a low Rbb' transistor can get well under a nanovolt.

Cheers

Phil Hobbs

es.

And there are also the Analog Devices XFET references

The National Bureau of Standards stacks up Josephson junctions, but that is n't a low power solution.

That does make sense. The result seems to be much the same as Kevin claims at

but the explanation is a whole lot more intelligible (for me at least).

Exactly.

I will say, that I did not invent the techniques that solve this x10 gain problem, but in practice, implementing known techniques involves a lot more than knowledge of just the basic ideas. What I am surprized though, is that the likes of Analog Device are clearly not implementing known techniques to achieve vastly superior performance.

and.... I am limited, as most are, to *standard* fab processes. Also, a 7V zener aint going to cut it with a 2V7 min supply requirement.

The likes of Analog Devices have access to their own special processes.

The problem is when you need low noise at 1Hz. A 1,000u cap is not commercially viable for the products I am designing.

Filtering only works at higher frequency.

I am targeting the 1 Hz offset phase noise on a 10MHz oscillator at something like -130dBc.

-- Kevin Aylward

Yes it is for the constraints that are pretty much universal in practical, commercial product.

I won't go into the detail right now, but I can't afford more than a few mA in the limiter.

e.g. 1 mA is around 1 Deg increase in temperature. A typically OCXO might have its xtal at 92 Deg.

You can't regulate the heater below the operating power of the ASIC. The output buffers can use 5 mA for starters.

And don't make me laugh :-)

Been there, just haven't wrote the book....

That device has 70nV/rthz at 10 Hz. It relies on a big honking capacitor of

Its regulator current is extremely noisy. It just filters it. Its raw, unfiltered value looks like around 5 uV/rthz at 1 Hz.

I am looking for 100nV/rt hz at 1Hz, with only a few 0.1uf capacitors in the oscillator package, which might be 5mm X 7mm

My BG get 50nV at that low current, with no capacitor. It uses a couple of ext caps in order to get its 80dB PSR at 1 MHz.

Look. I have literally, investigated 100s of BG topologies, over several calendar years, and 100,000s of simulations. I am a leading expert in BG design. It's a fact. Take that as you will.

See above, the *BG* in the LT3042 is s*it for noise.

In the real would, there are many, many people very skilled in what they do. Most don't write books or application notes.

The idea that some few golden oldies are the only experts is both arrogant and naive.

Widlar was a very, very impressive guy. The point I am making is that it is just a fact, that the design techniques he used then, have limited utility today.

He did what was optimum then. Today, we have vastly better processes, immense computer power,and the cost of 10,000 transistors, even at analogue sizes < 1 cent.

What took him 170 hours of continuous experimentation, I can set up in Cadence to do, and run in a few minutes.

The fact that Widlar *might* do vastly better designs today, with new tools, is not relevant to the fact that I am doing designs, today, vastly superior to what he ever achieved. I get paid for what I achieve today, not whether a dead person, may or may not achieve if he were alive.

What I will say, is that the mind set that I have is correct for todays technology. I understand that there is usually, zero value in designing a circuit with 3 transistors, rather than 50, if the 50 transistor circuit is either quicker to design, more reliable, easier to design, easier to validate or has higher performance etc.

-- Kevin Aylward

Well.... I have been 10 years specifically designing oscillator ASICS, in a company (Rakon) producing oscillators for 60 years, with a library stacked with books on oscillator design. I have personally went through 100s of topologies...

The issue with your comment, isn't that, sure, maybe there is a better solution, but that it implies an unwarranted assumption that certain others are too clueless to have come up with an optimum solution themselves.

As I said, it's *theoretically* impossible to design high stability oscillators without regulating the ps, and its trivial to do the math to prove this. "Captain, I cannie change the laws of physics, I need my 30 minutes."

We target 0.1ppb for a 5% ps change. If the current or voltage in an oscillator changes, the frequency changes. Its that simple.

Interesting idea, but not realistic in an ASIC. Transmission line delay lines probably is the only way to generate delay without adding excessive noise. Active delay amplifiers are a complete non starter, explained below.

Modern design needs solutions that exist in semiconductor ascic.

The problem is the inherent noise of the comparator transistors.

The input comes from a highly band-limited xtal filtered output. It can be shown that an ideal band limited input to an ideal comparator, has the same So/No as the Si/Ni. See for example:

The issue though, is that it is impossible to band limit the internal noise of the limiting amplifier. The net result is that the internal wideband noise, generates around 12 dB more output phase noise than would be expected from its amplitude noise. Its about power.

Every 1 mA might give about 1 Deg increase in temperature of an OCXO system. A 5 deg increase might have the system running at 110 Deg instead of 105 Deg. Its a major problem for the xtal. A lot of systems have the xtal at, maybe 90 Deg. The system loses regulation at its internal idle current level.

Oh... well those ideas have generated designs with 12dB lower noise than the competition.

So, yeah... I am on to something...and... its not my problem that others don't understand the theory.

The best ideas are not always patented. Its called, keeping a secret.

Seriously, there is no way I can post either my BG regulators that beat commercial BG regulators by orders of magnitude, or my oscillator designs, similarly 12 dB superior in noise to the competition, because they are not patentable. However, clearly few, if any, are using the specific structures and operating conditions the way that I am using them.

I have seen many of their patents. Truly a waste of paper for most.

I already noted that Gilbert had a design for a 3rd order approximate chebychev function, this was actually in a patent he had. No competent designer is going to use that approach in a high performance TCXO/OCXO. I just don't have the time to go into all the technical aspects of ASIC design.

Usually, a patent is where the author is simply unaware of how others solve the same problem in a standard topology.

The vast majority of patents are worthless. Big companies don't care how much they lose in getting patents for obvious ideas. They are just sticks to threaten people with.

-- Kevin Aylward

One dumb thing that a lot of startups do is spend a fortune getting a lot of silly patents. Well, maybe not totally dumb, because it does impress some investors. But it soaks up the energy of the innovators, not to mention a heap of money.

We just keep things private and invent new stuff faster than the competition can reverse engineer the existing stuff.

They have a jfet bandgap-sort-of reference that's awfully good.

I have seen that one. Its impressive.

Its why I stated BG (sum of dVbe and Vbe). I am aware of some of the other techniques that take advantage of special processes.

I am stuck to a commercial BiCMOS process. I chose a good one, but it still has limitations. It would be great to have SiCr resistors from another process.

-- Kevin Aylward

Would it make sense to use a higher frequency crystal, then the comparator, and divide the digital output? Or even a PLL and bandpass filter, then the comparator? Faster edge rates into the comparator reduce noise.

We did this series of tests by walking clock and data edges across one another into a fast D-flop, and averaging the output states.

Jitters are around 50 fs RMS, some of which is probably artifacts of the instrumentation.

The trick here being that we had fast edges going into the two ADI comparators that generated the walking edges.

A passive bandpass filter could slam lots of voltage into a comparator. But inductors are big.

As I'm sure you are aware, there are five principal reasons to get a patent: 1 an egoboost or career boost 2 to profit from the invention being used by others 3 so investors in a company have something "tangible" to sell to another investor 4 pile 'em high patent portfolio swaps 5 to prevent other people patenting it and stopping you from exploiting your invention

Some are more justifiable than others, and there are cheaper ways to achieve the last one.

w much

threaten

isn't five covered by selling stuff? i.e. if you can prove you have sold something that does what someone later tries to patent it is considered prior art and can't be patented

IANAL, but the essence of patents is disclosure of the techniques involved. I doubt simply selling an item is sufficient. OTOH publishing a technique certainly is sufficient, and is much cheaper.

I believe there are publications regarded as normal channels for that. I doubt anyone reads them, so it might be considered "security through obscurity".