FR-4

I'd love to see the dielectric constant measured accurately from 100MHz up to 20GHz for FR4 and FR408HR.

I'm convinced that the largest factor for loss of valid data time (aka 'closing of the eye') for high speed digital signals is due to change in Er with frequency. The loss tangent certainly tends to reduce the height of the eye, but the smearing in the time domain, due to arrival time differences from varying Er, really shuts that eye down. In my simulations, it has more of an effect than reflections due to via stubs - as long as they're reasonably controlled.

Bob

Microstrip is inherently dispersive. And the copper is lossy, especially when they treat the downside with that "black oxide" gunk, to make it stick to the epoxy better. I swear I can see the glass weave pattern in some TDR tests of FR4.

Past around 3 GHz maybe, things get nasty. Keep the traces short!

John

Hmm..FR-4 from ExpressPCB measured 20pF/sq inch (30 mil thickness).

Do you consider the roughness of the laminate? Apparently the fancy expensive HF material gets, in part at least, their lower HF loss due to a much smoother surface.

I _DO_ believe one can see the glass weave pattern using appropriate test strips. I think there was an article on that in (??) CircuitTree mag.

It is a known issue that the PCB material is anisotropic wrt the direction of the glass lining. The FR4 is indeed lossy. For that reason they prefer non-lined teflon or ceramic PCBs for RF stuff, especially if you need to do resonant strip circuits. Teflon and ceramics are nasty for machining and drilling.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

John,

How did you measure this?

There is regular debate on comp.arch.fpga on the effectiveness of using ground planes for high bandwidth decoupling with just bulk capacitors on the board.

It would be interesting to measure the capacitance at different spot frequecies.

Although 30 mils is pretty thick between the planes.

Nial.

I just sheared off a square, about 6 square inches, soldered wires, and measured it on my AADE c-meter. I stripped the copper in one corner and measured the dielectric thickness with calipers. That may have underestimated the thickness a little. I was mainly interested in the capacitance TC. I did a test on 62 mil FR4 some years back and got closer to +900 PPM/K.

That debate is endless. Based on many bare-board TDR and running-board noise tests, not to mention hundreds of working designs, I agree: the planes form a nearly perfect capacitor. Adding bulk caps, anywhere on the board, makes the planes look like a bigger perfect capacitor.

I keep ratcheting down the number of caps per FPGA supply. Three caps per supply pour seems fine. I'll try two next.

A 20 GHz TDR of a multilayer PCB power plane:ground plane system (with an SMA designed in for that purpose) is remarkably uninteresting. There is the usual connector launch wiggle, then it looks like a big cap, with subtle or no edge reflection effects.

Agree, 5-10 mils is better. I just had some 30 mil copperclad handy.

John

I recall reading about that. The advise was to keep tracks at a 45 degree angle with respect to the glass weaving.

John Larkin Inscribed thus:

A good few years ago I needed a 40pf standard and used a one inch square of FR4 to do it.

The epoxy used to bind the laminate weaves and the fiber diameter of the woven fabric all matter. I am surprised that with all the fiber strand advancements made over the last few decades that folks have not experimented with other media. I have seen some really weird boards from places like Loral and Titan, and what not, during my contract Mfg years, over a decade ago.

I can understand this working where you have large planes distributing say 3.3V throughout the board.

What about the 0.9V/1.2V/2.5V routed 'planes' you need to supply the multitude of voltages some FPGAs require?

Nial.

What's the Q of the 6 square inch FR4 capacitor? How about a 1 square inch FR4 capacitor? MikeK

No big deal. Use one solid ground plane. On the layers above and below, use power pours to get to the FPGA power pins. You can generally distribute two voltages per layer, and maybe even squeeze in a few traces. The pours don't have to be full planes; they just need to be big enough to reach a few bypass caps. It's nice to have a, say,

Here's an 8-layer board with 3.3, 2.5, and 1.2 going to a BGA FPGA and a DRAM.

ftp://jjlarkin.lmi.net/V490_pours.jpg

A great deal of the published stuff about high speed bypassing (use three caps, different values, per power pin! 200 caps per chip!) and routing ("return currents") is nonsense. HoJs's "Black Magic" book is half pretty good stuff, half nonsense. If you can tell which is which, you don't need his book.

John

Just use 0.33 uF 0603 bypass caps.

John

Our guys prefer 0402 because they route on a 1mm grid (the FPGAs). We do 'via in pad' so they can stick caps right on the back sides of the FPGAs.

Bob

The common habit of placing a large and a small bypass cap side by side makes for nice little tuned circuits, as the small cap resonates with the inductance of the large one. Apparently...

Above _and_ below?

:-0

You are spoilt with your multitude of power routing options!

I normally get away with one power plane for the two or three most commonly used/highest current supplies with polygon pours in signal layers to supply the rest.

No problems so far.

Nial.

---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 516 8883

Our manufacturing people don't like 0402s because they tombstone occasionally. We put the caps outside the FPGA footprint, preferably on the top side. Seems to work fine.

John