Fastest way to run a software feedback loop?

Altera seems to keep theirs around for several years, anyway. Xilinx has been iffy with their Coolrunner series, IMO. In any case, there is a better chance the low-end, like CPLDs will be around longer than the high-end stuff. Other than some military parts, those things change faster than womens' fashion.

There are mixed signal FPGAs now. Haven't used one, so I don't know how good they are.

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But they are not cheap. Probably double the cost of a high end micro. BTW, I am running a 96MHz PIC32, roughly equivalent to a

120MHz ARM M3. I read that someone is running 120MHz PIC32 in RAM, or 160 DMIPs.for less than 10 bucks.

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Which PIC # please? I would like to look at that.

Jamie

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Yes, you are right. Could be more, much more. The only pricing I can find online is a 600K Actel Fusion on Avnet, listed for $155.

Yes - I have been running an algorithm at 500kHz sampling on a 44MHz ADUC7021 for a while now (ARM32). It ran at 1MHz too but had no time for anything else. The STM32F2 replacing it runs at 120MHz (CortexM3), There is a 168MHz STM32F4 part (Cortex M4). All single chip microcontrollers.

[...]

--

John Devereux

How does that compare to execution speed of real C code? PIC32 is MIPS based. Since MIPS is not mainstream and ARM is I'd expect the compilers for the latter to be more efficient.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

On a sunny day (Mon, 17 Oct 2011 08:38:08 GMT) it happened snipped-for-privacy@puntnl.niks (Nico Coesel) wrote in :

My gcc MIPS version is really OK.

Cray 1 was not mainstream either.

PIC32 has 5 stage pipeline. ARM Cortex M3 (ACM3) has 3. ACM3 is not bad, but PIC32 does not suck too badly either.

Compiled from pic32-gcc:

Around 3 millions C +=3D A * B per second at 96MHz running from flash, where A, B and C are 32 bits memory buffer.

People have it running 160MHz in the fridge (for cooling).

But they had loads of money to spend. AFAIK Microchip has made some proprietary additions to GCC for MIPS but the effort is nowhere near the effort that is being put into GCC for ARM.

A deeper pipeline isn't always better. Google for MIPS and 'one delay slot'. You'll learn two things: jumps and calls may be costly and never try to program assembly on a MIPS cpu.

I have been down the MIPS road and quickly discovered there are very few people you can ask for directions.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

M, or

t

I don't plan on doing too much assembly, that's why we PICk on RISC in the first place.

There are too many forks (roads) for ARM. I/Os for STM is not necessary the same for NXP.

There are times for ARM, but should not rule out MIPS yet.

I am still looking into the PIC32 A2D. Perhaps we can get close to

2,000,000 samples per second.

Just be happy they use the same CPU core nowadays. In the old days each vendor had his own core complemented by a crappy toolchain. Ever chased a bug caused by an error in the compiler?

Using the peripherals is usually easy. Both ST and NXP have a large library on their websites which can serve as an example.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

end

to a

in RA=3D

MIPS

=3DA0ACM3 is no=3D

Just so long as you do not assume that the examples are bug free.

?-)