Energy usage in electronics design languages

The power requirements for different parts of a processor will be heavily dependant on the implementation - you are not going to be able to build different parts on different FPGAs and find out anything meaningful about the power requirements of a complete processor made using standard processes.

Assuming you don't want to go to the expenses of serious full-scale simulations, the easiest way to get at a vague idea would be to implement the processor parts in an FPGA and use the design software's power estimators to give you a guess - the Altera Quartus power estimator is, I believe, the most accurate at a sane pricing level.

Thanks for the answer. However I don't think I was very clear on my initial question.

I am interested in optimising software, rather than hardware for energy consumption in an online fashion (by a loose form of economic evolution). A program is instantiated over many message passing concurrent very small fine grained parallel processors with a tiny bit of memory (a bit like smart memory).

This is getting a bit beside the point I want one program to be able to read how much (software dependent) processing is being done by processors in another area . So I was going to group processors in to areas with a common power rail and monitor the energy usage of that group and have that as an Input to the system, the more processing the more energy usage. So I was wondering if there were EDL that allowed this kind of design.

Thanks again for your help. I will want to make sure the processors process efficiently as well as having efficient software on them.

Will Pearson

A profiler?

Good Luck! Rich