dsPIC33CH Vs dsPIC33F divide.

No, there are plenty of clever people on comp.arch.embedded. But they tend to stick to on-topic posts, and ones that interest them. I don't expect there are a great many people using the dsPIC devices, and I expect very few of these people are interested in how the new versions do their division. They might be happy that new versions are faster at division - but why is it of interest /how/ this is implemented?

Division hardware can be implemented in a variety of ways - wikipedia will give you some suggestions. And if you are really interested in the details, comp.arch is a better newsgroup.

So you don't know either and you don't want to know, thanks for that insight.

It doesn't really help, unfortunately.

Thanks.

Cheers

I know some ways of doing division in hardware, and I know where to look for more details. (I've pointed you at a couple of good starting points

- one website, and one newsgroup.)

I haven't the faintest idea what method is used in the dsPIC devices, and I don't expect anyone outside the inner circle of Microchip's design team know either.

Does that help?

Another possible choice would be comp.arch.fpga. Those folks don't make chips like the dsPIC, but they make algorithms in FPGAs.

Clive Arthur wrote

I am looking at the datasheet, and indeed it says on page 1

But searching for 'cycles' in the pdf finds this on page 45: 3.1.8.2 Divider The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes:

The 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend.

The divide algorithm takes one

We have gone to The Dark Side and do most embedded-system math in floats these days. Some of the modest ARMs have hardware vector fp.