dsPIC AD converter input impedance

Be sure you lie flat on the floor if you read about the ADC ST put in their STR700 series microcontrollers. For starters (!!) it has an internal reference voltage with an accuracy around 10% (IIRC). In short the whole thing is a complete joke. After that I never considered controllers from ST for any design.

Probably a glorified diode :-)

And then there are some Asian uC where the documentation consists of a few pages, mostly listing local offices and their phone numbers.

I found that TI documents their stuff rather well.

Make no assumptions. There are MCU families with the ADC equivalent input resistance anywhere from 10K to 10M, not considering the dynamic settling time.

Paradigm: programming for a chip is chip maker responsibility.

???

1. TI documentation for new DSPs sucks.

1. TI has a habbit of telling one thing in exactly one place in the datasheet. Such as if they describe a peripheral configuration register, they describe only config bits that are relevant to this peripheral. All other bits of this register are grayed. It is somewhere in the datasheet, but you have no idea where to look for their definition.

VLV

Luckily, chapter 7 in this tutorial provides some more detail:

For example, that 2.5k source impedance can suffice. I am below that but have a 1uF cap in addition.

Or sometimes, you can get all the information. But only if you know the owner for at least a decade and are married to his niece :-)

Page 28 is what I call a good summary of ADC input characteristics. On typical values give for input impedance but that's ok. The dsPIC datasheet is a far cry from there.

AFAIK NXP still provides an equivalent circuit for ADCs in their micro's.

The provided worst-case leakage current spec will limit you to a few K of source resistance for +/-1 LSB error . If you like to play the odds, you can try going higher..

That won't be a concern because I am slghtly below 1k. But it would have been kind of practical to know how much internal resistance is going to be in parallel with my 1k. TI provides such information right in their datasheets. Such openness has been rewarded with numerous design-ins so far. Oh, and the pizza at the seminars was pretty good, too :-)

I certainly have. We've had the factory folks in flogging these things. They finally said "lets try all combinations". One problem was never solved. It took hardware. We weren't the only ones who saw the problem, but according to the vendor "no one else has reported the problem". Yeah, right.

BTW, the company lost upwards of two years trying to track these problems down. Some of the problems are still only papered over. They come back to haunt every so often.

The model for an unbuffered switched-capacitor ADC input really does not look like a simple resistor, so a model with parameters makes a lot more sense to me.

Here, right from the data:

... PDF page 391.

The details become especially important if you're using more than one channel.

Best regards, Spehro Pefhany

Multiplexers first, then a PGA, then the resistive divider into the ADC. The evil cap was on the divider output.

Overall it's 64 differential channels, in groups of 8. A group of 8 customer inputs feeds an 8x2 diff mux, unity-gain follower fet amps (a whole nother story), an AD8253 PGA, a resistive divider, and into one input of the ADC. We actually used two of the AD7699s, only 4 channels on each, to keep the speed up. The timing is sort of hairy, what with all the scanning, settling, serial ADC stuff, gain switching per-channel, node discharging, and digital filtering.

Makes me glad I never learned VHDL.

The AD7699 is really nice. We've used it several times before.

Doesn't seem to depend on other channels, but we didn't try sequencing other than dumb sequential. We did take care to discharge some nodes in the mux array, to reduce channel crosstalk, but that's ahead of the ADC.

Mux'd ADCs are non-trivial, past maybe 10 bits.

John

There is a model of the ADC input showing +/-500nA leakage and the 4.4pF (18pF in 12 bit mode) sampling capacitor with an indication of the maximum internal series resistance. The sampling time depends on how software configures the ADC. The recommended 200 ohms probably covers the sample time required for its maximum 1.1 MSPS conversion rate.

Oh, one other gotcha about this ADC. The "Negative or COM input, bipolar mode" spec is serious. If you plan to do bipolar inputs, the low side has to be almost exactly Vref/2 or nasty stuff happens. The inputs are not differential in the sense you'd expect on most ADCs.

John

That's the circuit I found in a tutorial. Hoping it's the same on dsPIC. It would be kind of nice if they had at least a little more meat in their datasheets.

Probably also how often that C-hold is accessed.

So no I have three pieces of information. Datasheet sez 200ohm, some other paper sez 5k, and your link (note 3) sez 10k. Wot a mess :-)

Almost certainly not- the hold capacitor value varies widely between families, IIRC. The above reference is for a practically obsolete

You need to refer to the appropriate reference manual for the dsPIC, not the midrange reference manual. PIC30 may be different from PIC33 as well.

The total documentation is well in excess of 1000 pages- the data sheet is just a brief overview, with some chip-specific characteristics. It's like the ARMs and other micros- not everything is in one place. Or consider the data sheet the user manual, but as competent engineers we want to see the service manual..

They've broken the reference manuals up by chapter in the latest chips, you can't even download it all in one chunk AFAIK.

Exactly, on the conversion rate. The Chold cap is _discharged_ prior to conversion so it's proportional to the conversion rate.

I don't see a mess- just different chips and situations.

Understood. However, we live in the age of cyberpower, post-Tricorder, where lots of storage space and bandwidth is available, teens stream gigabytes of MTV shows, and so on. So I'd have expected that a search would lead to what you find at TI: Datasheet, family spec, app note links, all nicely in one place. Or at least a hyperlink in the paltry AC section of the datasheet linke IEEE does, "to probe further". But no ...

We can be super slow on that, once a second is enough most of the time. Faster rates a well but that's only for trending where absolute accuracy is not important. In this application a dsPIC is like driving a 5-ton truck to bring three letters to the post office. It wasn't my pick. Or PIC :-)

Well, my definition of an orderly assortment of technical documents appears to differ from Microchip's :-)

I've found Atmel datasheets are very thorough and specific. Sometimes too specific, because all the verbiage for say timer-counters 0 through 2 all use the same text, with subtle variations appropriate for the section. But overall, you don't need to read anything that isn't in the section at hand.

Too bad Altera isn't as specific on their FPGAs, or anyone else for that matter.

Tim