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Darlington driver interfaces with mixed voltages

I'm planning to use a ULN2003 7-way darlington driver as an input/output isolator for a FPGA with 3.3v I/O. The input interface has pullups from the collectors to 3.3v supply, and the output base inputs are driven by the gate array output lines, and switch loads (relays and LEDs) to a 12vdc supply. Total i/o count is 6, so one 2003 will do the job, however I'm wondering whether the common diodes on the collectors inside the 2003, combined with the dual voltages involved, might pose a problem. If the diodes were 'perfect' the situation would be OK, but things aren't often that easy in the real world.

Can anyone see any shortcomings? TIA

Ascii schematic for clarification follows.

3V3 3V3 | | | 12VDC .-. | \ | | | _ o o | | .----------------. )| '-' | | )| |---------| | _)| | | | |/ | FPGA | |/ -| | |----| |> | | |>

| | | | | | '----------------' (created by AACircuit v1.28.6 beta 04/19/05

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Reply to
Bruce Varley
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=A0 =A0 =A0 =A0 =A012VDC

=A0 =A0 =A0 =A0 =A0 =A0 =A0\

=A0 =A0 =A0 =A0 =A0 _ o o

=A0 =A0)|

=A0 =A0| =A0 =A0 =A0 =A0)|

=A0 =A0 =A0 _)|

=A0 =A0| =A0 =A0 =A0|

| =A0 =A0|/

=A0 =A0|----|

=A0 =A0| =A0 =A0|>

=A0 =A0| =A0 =A0 =A0|

=A0 =A0|

The only shortcoming with this kind of driver is the relatively large dI/dt on the 12V and return board traces when the relay current is abruptly cutoff by driver(s). One way around that is to hang a zener or other type clamp off the COM pin to GND. This forces the relay to discharge its current through the 12V feed, greatly attenuating the EMI. Something like the 1.5KE16A with 13.6V standoff rating should work.

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-hard to say without knowing your loading.

Reply to
Fred Bloggs

Looks good to me. I assume the diode common rail of the ULN is connected to +12.

John

Reply to
John Larkin

Make sure the COM rail is bypassed really well.

Also, keep in mind that these are Darlington stages so the output won't pull much below 800mV. If the FPGA has the logic thresholds in the middle and not too extreme of a hysteresis on that you should be ok.

--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

As others have said, you can connect the diode common to +12 or to a clamp. Using a single ULN2003A, I would connect the diode common to

+12 to prevent capacitively coupling spikes through the reverse biased diodes to the FPGA inputs when the relays switch. Hopefully, the 12V is regulated and otherwise well behaved and not something naughty such as an unfiltered vehicle "+12V" rail- that could be a good way to kill FPGAs.

Watch the input levels on the FPGA (and how it is configured)- it's not uncommon to have FPGA Vinl specified at 800mV with a 3.3V supply, and the darlington won't reliably achieve that. It'll probably work in the lab, but there won't be guaranteed margins.

Best regards, Spehro Pefhany

--
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

How could the feedthrough due to clamp be any worse than the collector flyback thru the diode to 12V?

Reply to
Fred Bloggs

|| +----------- -||-+---------+ |-+ | (0V->30V->0V) | | | | | | | | - / | +--- ->|-+ / ^ eg. 30V clamp TVS In | | Out | +3.3 +-------+ | | | | +----- === | | | | | GND - | |/ |/ C| ^ | -| -| C| FPGA | | |> |> C| Relay coil CMOS | | | | | INPUT +----- | | | === === +12 - GND GND ^ | | === GND

If you don't tie the diode common to a fixed voltage, you get a high dv/dt at the common which couples into the input through the diode capacitance.

Joerg's point is well taken too that the relay ground current could cause bounce that could glitch the inputs or worse. Usually there's a solid ground plane with FPGAs, of course, so reasonable relay currents shouldn't cause problems, assuming sensible layout.

Best regards, Spehro Pefhany

--
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

=A0 =A0 =A0 | =A0 =A0 =A0 at common

=A0 =A0 =A0 |

->0V)

=A0 =A0 =A0 =A0 |

=A0 =A0 =A0 =A0 |

=A0 =A0 =A0 =A0 - /

=A0 / ^ =A0eg. 30V clamp TVS

=A0 =A0 =A0|

=A0 =A0|

=A0 =A0=3D=3D=3D

=A0 =A0 GND

The diode anode is connected to the Darlington collector, so you already have a large collector dv/dt going thru Ccb to the input. There's also about 15pf of substrate capacitance at the input pins according to the data sheet. Then the 2003 has about 2.7k in series with the base. If the difference between the COM to clamp versus COM to 12V makes or breaks the FPGA then the ULN2003 is not the part to use anyway.

Well that's just the thing with the clamp, all the transients are in series with that big klunky relay coil, there will be no GND spikes. You can't say the same for COM to 12V=3D large di/dt's.

"The Journey is the reward"

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eff.com

Reply to
Fred Bloggs

=A0 =A0 =A0 | =A0 =A0 =A0 at common

=A0 =A0 =A0 |

->0V)

=A0 =A0 =A0 =A0 |

=A0 =A0 =A0 =A0 |

=A0 =A0 =A0 =A0 - /

=A0 / ^ =A0eg. 30V clamp TVS

=A0 =A0 =A0|

=A0 =A0|

=A0 =A0=3D=3D=3D

=A0 =A0 GND

"The Journey is the reward"

formatting link

eff.com

How about this: Please view in a fixed-width font such as Courier.

. . . +12V . | . | . [10K] . | . COM | . +----------||----+-----+---. |----+ | | . | | | =3D=3D=3D | . - | | 0.1| | . ^ | | | - / . PGA | | +--- ->|-+ | / ^ 13.6V clamp TVS . MOS | |/ | | | . NPUT +-[2.7k]-| | Out +--- . | |> +----- =3D=3D=3D . In - | | | GND . ^ | |/ C| . | =3D=3D=3D -| C| . | GND |> C| Relay coil . =3D=3D=3D | | . GND | . =3D=3D=3D +12 . GND . .

Reply to
Fred Bloggs

=A0 =A0 =A0 | =A0 =A0 =A0 at common

=A0 =A0 =A0 |

->0V)

=A0 =A0 =A0 =A0 |

=A0 =A0 =A0 =A0 |

=A0 =A0 =A0 =A0 - /

=A0 / ^ =A0eg. 30V clamp TVS

=A0 =A0 =A0|

=A0 =A0|

=A0 =A0=3D=3D=3D

=A0 =A0 GND

"The Journey is the reward"

formatting link

eff.com

put a resistor in series with the fpga input, xilinx generally spec spec that you can do pretty much what ever you want to an input as long as you keep the current under ~20mA

-Lasse

Reply to
langwadt

Do you mean the FPGA output? I'm not worried about that- it has a series resistor and is shunted by Rds(on) of the ouput MOSFETs. There is probably only mV there, if that. I'm concerned about transients conducted from the diode common right into the FPGA high impedance inputs when the input transistor is 'off'. It's probably okay if the pullup is kept really low, but say the diode cap is 5pF and the dv/dt is 50V/usec, then you can get 1.1V of glitch with a 4.7K pullup.

Or splurge the extra 20 cents and use two of them. Then less grounding worries and no glitch worries, and layout is less icky with 3.3V FPGA inputs a few mils from high current 12V outputs so a probe slip terminates the FPGA. And using a clamp as you suggest is better for the relays anyhow- it's exactly what I normally do.

True.

Best regards, Spehro Pefhany

--
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

He wants to take a signal from the outside world and feed it through a ULN2003A inverter to the FPGA input, so the part on the left isn't quite right.

Yes, I think the 0.1uF + precharge resistor will work fine.

Best regards, Spehro Pefhany

--
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

I'm not seeing a conductive path from the driver COM to an FPGA input???

Reply to
Fred Bloggs

Never mind- I just re-read his OP...

Reply to
Fred Bloggs

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