D-latch's propagation time?

Well, since nothing happens on the negative edge, you might seriously consider the other one.

John

Depends ;-) Some old-style CMOS were negative edge triggered.

...Jim Thompson

That depends on the logic family. I have some that are specified as 330ps (MC100EP52D), but other families are somewhat slower. How about having a look at the datasheets ?

Rene

But the OP implied positive.

Early 7400-series JKs used neg edge clocks, probably with ripple counters in mind. They also tended to do "ones catching" which caught a lot more than one young engineer.

John

"Positive level trigger" is a tad ambiguous.

Sort of.

I've found that there occasionally comes a time when reading datasheets can be helpful.

John

Around here, admittedly an engineering backwater, "latch" is sort of synonymous with "register", not too specific. It's also a verb, "latch all that stuff for the CPU to snoop." One says "transparent latch" when necessary. Actually, transparent latches can save a lot of time, namely one full clock, in lots of situations, even though they can get you excommunicated from The Church of Synchronous Design.

When I went to engineering school, lo many years ago, I don't think we saw a single actual commercial datasheet... everything was abstract parts in textbooks. Is that still the case?

John

Dunno, he said "positive *level* trigger D-latch", which to me indicates a polarity-hold (a.k.a. "transparent latch"). At some point on the negative edge the latch will become transparent, so it is doing something. ;-)

Sure, but then to me, so is "edge triggered latch". In my personal dictionary, "latches" are level sensitive and "flip-flops" are edge sensitive. ...but admittedly that may be just my background.

So in the above question, "level" and "latch" go together (~level sensitive) and the odd man out is "trigger" (~edge).

Didn't see one, but that would make the homework too easy.

Sure. They usually post at the last minute, in desperation, and we never hear from them again, unless you count "want fries with that?"

Actually, I've never formally studied logic design or programming... I just sort of started doing it. A couple of ex-TIers showed me the synchronous-logic orthodoxy one afternoon (they always strapped presets and clears high... through resistors of course... wouldn't even use them on powerup) so I divested some of my worse habits along the way.

I mean, logic is pretty obvious.

John

Bwahahahahaha! Good one!

That's what the GenRad logic guru always enforced on me... tie off all unused inputs thru resistors... makes debugging real easy.

...Jim Thompson

A "register" 'round here is a group of flip-flops or latches. I do sometimes hear "latch the bus, on...", but in more precise circles it's "register the data on...". Of course edge-triggered is verboten!

Not in these circles. It's all level-sensitive (LSSD design rules), though two latches in a row clocked off opposite phases rather looks like an edge-triggered master-slave FF from 20K'. ;-)

I was referring to the OP's transparent request for homework help.

Dunno what they do now (seems it's all C++), but 30+ years ago at UIUC we built real hardware, using real datasheets. You didn't go to the Church of the Holy "Mustard Bible"? I wish I still had my first (and second) edition. They might be worth something today, but kept sprouting legs. :-(

I suggest you learn to read a data sheet.

Good Luck! Rich