Larkin
=20
=20
Even though i am nearly a week behind, i gotta step up to the plate.
The most common form of core memory is called 3D. It is made up of bit planes (the third dimension). The cores have a very square B-H curve. In the bit planes there X and Y direction drive wires. Coincident current through the two wires produces enough field to make the addressed core switch direction of magnetization. The current pulse times are usually no longer than enough to ensure reliable operation. No other cores in the plane receive enough drive current induced flux to change state. Thus we need to add a sense wire to detect the core flux state changes. The sense wires are typically done diagonally to take advantage of the slightly larger aperture in that direction. =20
Since the mechanism to readout the value of the core forces it to either the "0" or "1" state (a design property) any information to remain in the address must be rewritten. Thus another wire called inhibit which is wired in parallel with either the X or the Y drive lines and is driven with an opposing current flow which prevents changing the state of the core on the writeback half cycle. =20
This allows three typical cycles read-writeback, read(erase)-write, and read-alter-write. These are the external interface definitions and read-alter-write may not be implemented.
I hope that have not omitted too much.