CGW glass-dielectric capacitors

I have around here, somewhere, a paper where they make a lumped L-C delay line using some sort of ceramic caps. The caps are sufficiently nonlinear that they get a shock-line effect that dramatically sharpens the risetime of an edge as it propagates through the line. It runs at something like the 2KV level.

John

Le Mon, 05 Nov 2007 07:43:52 -0800, John Larkin a écrit:

Certainly not C0Gs.

I've once had the idea of using some Hi-K ceramics to toy with this but... too much of productive work. Maybe one day.

Hi-K ceramics have some funny behaviour, like ESR dependance on voltage, time relaxation of capacitance and ESR after temperature or voltage stress,...

I haven't done the experiment, but I would guess that inductors are less ideal than capacitors. Are you attempting to position the inductors so that they don't couple?

I recall in the dark ages the sine source used on HP ATE (as opposed to bench instrumentation) was around the -60db THD point. It was a pain that the bench instruments were not as good, i.e. they required passive filters to reach the same level. I was in design, not test, so I don't recall exactly the model of ATE, but I believe it was the HP