It's all working as it should now. Couple of track cuts and links to sort the P fet. It won't work with zero load on the O/P. 10K works fine.In the full circuit, load is at least 5mA from the receiver module. I had one other P fet in the circuit and I had to switch D-S on that. Worked fine when done. Thanks evryone for your help- especially ED for the LT sim confirmation that boosted my confidence no end.. Well happy.
A resistor source to gate will always turn it off.
John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics
All sorted, track cuts, links,all working. Definitely needs a load on the o/p to function. 10K worked fine. Plenty of load in the overall design (>5mA +)
With the exception of PFET wiring error, just exchange D-S to fix it, that's a pretty good circuit. TR1 /TR2 form a classic bistable latch, meaning turn it on and it stays on, and turn it off and it stays off. The actuating signal via SW-PB is momentary. Taking ON to mean TR1 is on and passing Vbatt to the output, the state is latched by the Vbatt output through R3 to the gate of TR2 turning it on and pulling the gate of TR1 to GND, reinforcing the ON condition. Cap is discharged to 0V in the ON state through R2 and the drain of TR2. So pressing SW-PB during the ON state causes the gate of TR2 to be discharged into the much larger 1u Cap. TR2 then turns off instantly, causing the gate of TR1 to be charged high through R1, turning TR1 off. Since Vbatt is removed from the output, the latching voltage through R3 is removed, and the gate of TR2 stays discharged, latching TR2/TR1 off. If you continue to hold the press on SW-PB, the gate of TR2 will be charged through R2 and R3/D2 to the output. The circuit will eventually go out of the OFF state and back to the ON state if Cap is allowed to charge to TR2 gate threshold. To prevent this, a loaded output limiting the Cap voltage to 0.2V will work. The series resistance is approximately R2= 100k, so Rmax, load= 0.2V/(Vbatt/100k)= 4.7kR should work. You can eliminate that 3/4 ma static loading in the ON state with another momentary, ganged to SW-PB. Or you can migrate to LVMOS logic for a bistable controlling the single AO3047, and have zero static loading in either state.
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