c question

It was the one you showed of the fpga, I think. It had lands for the chip to the right middle.

Have you seen the crap that tourists buy in Sausalito? I am pretty familiar with the art world...The pcb layouts have a "je ne sais quoi...Un rendez-vous avec l'esprit de la monde moderne." j

Given that the analysis tools are available, and that bridges have had that problem for millenia, that was just sloppy engineering.

I suppose each pedestrian might react to motion, and adjust his step, and become a small negative impedance coupled to the bridge's resonant modes.

I wonder if drivers in cars have any equivalent dynamics. Probably not. Probably they are self-damping.

We'll probably have the waveform player program sleep for a while, wake up and check things, initiate file reads, top off FIFOs, and go back to sleep. The sleeps would be shorter than the FIFO drain times, around a millisecond roughly. Interrupts are a nuisance.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

Programmer, over $100K plus substantial bonuses, medical, 401K. The FPGA guy is a consultant, and we fight over his rate. He wants $95 an hour, and I offered him $120. We compromised.

It's easy to include a FIFO fill count register, so the program knows how much room is left, and kicks off a loop to mostly fill it up.

The ZYNQ 7010 has 240 kbytes of sram. That's 30 kbytes per DAC, or 15K samples. We might plan for 4K or 8K to leave some room for other stuff, like ADC buffering later. 4K samples at 500 KHz is 8 milliseconds, which sounds OK.

So my wave player program needs to run at least every few milliseconds and not get suspended by any other processes for long.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

This one?

I like that one.

What do you expect, when a ferry runs a few thousand tourists a day from Fishermen's Wharf to Sausalito.

I was talking to some people, on a trip.

Where are you from?

San Francisco

Oh we love San Francisco... Union Square, Fishermen's Wharf

Have you been to Land's End and the Cliff House?

No, where's that?

Northwest corner, on the ocean.

You have an ocean?

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John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

One of these days, I'm going to write my own damn EDA software, that works. It's going to have a good looking library, and automatic placement / padding features on all primatives (symbols, wires and labels). A part or wire not where you want it? Don't just drag it, add hinting so it goes there naturally. It'll be LaTeX, for schematics, with better usability than Altium.

Well, a guy can dream at least.

Tim

--
Seven Transistor Labs 
Electrical Engineering Consultation 
Website: http://seventransistorlabs.com

I'm a bit puzzled as to why bother running the data through the processor. It would be child's play to hang a memory of nearly any size off the FPGA and let it address the memory directly. The memory can be loaded off line and played back at far faster rates than the rest of the system can support.

Why slow down the system with the comparative complexity of a processor and optimizing the C code involved? Adding one chip and a memory interface to the FPGA puts all the time critical code in HDL where it belongs.

--

Rick

Adding a memory chip would be like bringing sand to Sahara

It's a Zynq so the FPGA part already has full access to the 1Gbyte ram on board via several different interfaces, simplest seems to be this:

stream data from memory to userlogic, or from userlogic to memory

-Lasse

Would there be a way to throttle the transfer rate?

The DACs will be clocked by a DDS or some such, to play back waveforms at the rate they were recorded. We'll have a FIFO on each DAC, something like 4K or maybe 8K samples deep.

How will the DMA controller know when the FIFO is full, or close to full?

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John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

The answer is because Larkin likes to bitch about software in general and C in particular. It might be a cost constraint to do it on chip. The obvious way to do it fastest is by memory mapping in *hardware*.

I doubt it will make much difference to the speed but if it has to be shuffled from one memory location to another you may as well let the DMA controller take care of it rather than load up the CPU pointlessly!

CPU effort is then limited to keeping track of the pointers to next data. Incidentally an option to do periodic data would be sensible.

He likes inappropriate solutions. Note that he intends to *poll* the FIFO and have an actual depth to read rather than do an interrupt.

DMA would be an option with the architecture he specified and then offer

8 channels @ X MHz or 4 ch @ 2X or 2 ch @ 4X or 1 ch @ 8X Depending on how you alias the FIFOs into the memory map.

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Regards, 
Martin Brown

If the SD card is directly accessible by the FPGA, you could have the FPGA do direct reads on the SD card. We did this for a project were we were transmitting several MP3 streams which were written on the card. A FIFO between the actual reader module and the data user was necessary because of issues with block sizes which I do remember only vaguely. The card was written with a suitable dd command, i.e. no FAT32 there...

Pere

A slightly more subtle effect than that in that people left to their own devices tend to walk in lock step and have to consciously act to avoid doing so. It didn't help that on the opening day they had a competitive walking race across it which really set it boinging.

I found the story of the original bridge that led to the military breaking step when marching across bridges. It was a very early iron chain Broughton suspension bridge in Salford near Manchester. A platoon marched across it in strict time and it collapsed spectacularly.

Have you never seen a shockwave propagate back down a freeway? It happens when someone squeezes into a non existent gap with drivers too fast and too close together? It happens all the time on busy UK motorways. I guess US drivers change lanes less often and have many more lanes all doing the same speed so it might not be such a problem.

It only takes one with a club foot on the brake and a collision results. But either way a phantom shockwave propagates back down the traffic queue with brake lights going on for essentially no good reason at a speed determined by vehicle separation over reaction time.

Only a complete dork would do it by *polling*.

Interrupts are the right way to do it. Definitely more trouble and a bit tedious to get right initially but lowest possible CPU overhead and the right priority to grab the CPU as and when it really needs to.

Since you have this irrational abhorrence of software WTF don't you do it properly in hardware and memory map the FIFOs aliased consecutively and then set up a DMA controller to move blocks of data from ram to the memory mapped FIFOs which should appear as ABCDABCDABCD.

You can then do 2^N channels with max relative speed 8/2^N.

--
Regards, 
Martin Brown

Madness. The program only needs to know that there is enough room in the FIFO for another long block of data to be transferred.

What a waste! This is easy work for a DMA controller from ram to memory mapped IO (which could be mapped several ways to give 8,4,2,1 channels).

I'd be inclined to use 192k for the DACs 24k each for 8 (48k for 4 etc) and have the FIFO signal ready when a 64k/128k transfer is possible.

It should be the highest priority task but run for the shortest time possible. Much easier to do this by FIFO ready interrupt especially if it merely sets and updates a few parameters on a DMA controller.

--
Regards, 
Martin Brown

Modelling traffic flow leads to some really interesting math. If you plot vehicle flux vs traffic density, the curve goes from the origin (maximum speed but no cars), through a maximum, and back down to zero at traffic-jam density.

Near the peak, tiny changes in flux correspond to huge changes in density, and hence in average speed. Adding one extra car can produce a jam-up, and there are all sorts of nonlinear wave phenomena involved.

My senior-year PDE prof was an oceanographer who specialized in nonlinear waves such as Rossby waves and vortex formation at the edges of the Gulf Stream, so we had great fun in that class.

(You do tend to get a bit hooked in when John doesn't do things your way, I notice.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

What's dorky about runing a nice state machine every millisecond or so? Of the FIFO can hold, say, 8 ms of data worst-case, the efficiency loss will be mininmal. A state machine like that is easy to start, easy to stop, and doesn't require interrupt hardware or ISRs.

The right way to do is is what works best.

Definitely more trouble and a bit

I've written three RTOS's, been there, done that. A few compilers, too. All that has made me appreciate simplicity.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

And the fill count register tells it exactly how much room is left, and the program can decide how much to dump in to mostly fill it up. That's max insurance against running the FIFOS dry.

That would be a bunch of work, both for the DMA side in the FPGA and the Linux driver, building all those linked DMA control blocks, really a custom driver. This is a heap of work, and it's messy to both start up and shut down. We'll go with a state machine and see how it works. The FAT32 SD card read will probably be the throttle.

We have another project, a PCIe VME crate controller, that is awaiting enough engineering and programming horsepower to implement DMA. That gets priority, and it will be a lot of work.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

I was going 80 mph down a freeway yesterday - pretty close to average speed there - when a car in front of me swerves out a little into the lane - As I passed that person, I looked over, and the person was texting with a cell phone directly in front of their face. Laws vary by state and country. Maybe the trial lawyers block laws getting passed?

Yeah, direct DMA would involve dealing with the file structure. One could per-compute a chain of DMA descriptors, based on the FAT32 structure. What's the DMA page size in Linux? 4k bytes? That would be a lot of descriptor blocks for a

64 Gbyte file.

Linux already does all the nastiness to read files into memory. It's sure tempting to use that as-is.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

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So automate the test harness whiner. I developed that technique over 30 years ago.

?-)

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ays

e up and check things, initiate file reads, top off FIFOs, and go back to s leep. The sleeps would be shorter than the FIFO drain times, around a milli second roughly.

So your "nice state machine" generates the interrupt, but you don't set it up as interrupt, despite the fact that that the way that kind of intermitt ent process is supposed to get it's share of processor/bus time.

ill be mininmal. A state machine like that is easy to start, easy to stop, and doesn't require interrupt hardware or ISRs.

It's its own interrupt hardware.

You've got to think about how to handle them ...

ll that has made me appreciate simplicity.

My teeth always get set on edge when I read that kind of claim. What it usu ally means is that the claimant wrote several bad almost real-time-operatin g systems back when nobody really knew how to do it, and a couple of really dumb compilers, and hasn't got enough sense to hide these juvenile misdeme anors.

--
Bill Sloman, Sydney