An imaginary variable-voltage photomultipler power supply

I've now got a simulation of the variable voltage version of the Baxandall photomultipler power supply.

C1 has been pushed up to 3.3nF, equivalent to about half the 10pF inter-win ding capacitance of the output secondary L3. The leakage inductance of the transformer, even with a coupling factor of 99%, puts a bit of high frequen cy ripple on the output waveforms [V(ct),V(tank+)and V(tank-)]. Making C1 a n appreciable fraction of the reflected secondary capacitance lowers the op erating frequency appreciably - the circuit is set to run at 43.5kHz, when the original target was 100kHz - but it does tame the ripple.

Version 4 SHEET 1 2176 1652 WIRE -576 -208 -608 -208 WIRE -384 -208 -512 -208 WIRE -80 -208 -384 -208 WIRE 320 -208 -80 -208 WIRE 320 -160 320 -208 WIRE -384 -144 -384 -208 WIRE 1552 -80 1552 -112 WIRE 1728 -80 1680 -80 WIRE 1824 -80 1792 -80 WIRE 1904 -80 1824 -80 WIRE 2080 -80 1968 -80 WIRE 320 -32 320 -96 WIRE -128 -16 -288 -16 WIRE 112 -16 -48 -16 WIRE 272 -16 112 -16 WIRE 1680 32 1680 -80 WIRE 1824 32 1824 -80 WIRE 992 144 944 144 WIRE 1088 144 992 144 WIRE 1216 144 1168 144 WIRE 1264 144 1216 144 WIRE 1424 144 1344 144 WIRE 1472 144 1424 144 WIRE 1680 176 1680 96 WIRE 1824 176 1824 96 WIRE 1936 176 1824 176 WIRE 2080 176 2080 -80 WIRE 2080 176 2000 176 WIRE 320 224 320 64 WIRE 640 224 320 224 WIRE 752 224 704 224 WIRE 1120 224 832 224 WIRE 1216 224 1216 144 WIRE 1216 224 1120 224 WIRE 2080 224 2080 176 WIRE 944 304 944 144 WIRE 1152 304 944 304 WIRE 1472 304 1472 144 WIRE 1472 304 1216 304 WIRE 2080 352 2080 304 WIRE -608 368 -608 -208 WIRE 944 464 944 304 WIRE 320 528 320 224 WIRE 2000 528 1904 528 WIRE 2080 528 2080 432 WIRE 2080 528 2000 528 WIRE 576 544 496 544 WIRE 752 544 656 544 WIRE 896 544 752 544 WIRE 1472 544 1472 304 WIRE -32 608 -160 608 WIRE 176 608 48 608 WIRE 272 608 176 608 WIRE 1056 624 768 624 WIRE 1248 624 1136 624 WIRE 1424 624 1248 624 WIRE -160 656 -160 608 WIRE 2080 656 2080 528 WIRE -288 672 -288 -16 WIRE 496 672 496 544 WIRE 768 672 768 624 WIRE 1904 672 1904 528 WIRE -608 816 -608 448 WIRE -384 816 -384 -80 WIRE -384 816 -608 816 WIRE -288 816 -288 752 WIRE -288 816 -384 816 WIRE -160 816 -160 736 WIRE -160 816 -288 816 WIRE 320 816 320 624 WIRE 320 816 -160 816 WIRE 496 816 496 752 WIRE 496 816 320 816 WIRE 768 816 768 752 WIRE 768 816 496 816 WIRE 944 816 944 560 WIRE 944 816 768 816 WIRE 1472 816 1472 640 WIRE 1472 816 944 816 WIRE 1680 816 1680 256 WIRE 1680 816 1472 816 WIRE 1824 816 1824 176 WIRE 1824 816 1680 816 WIRE 1904 816 1904 736 WIRE 1904 816 1824 816 WIRE 2080 816 2080 736 WIRE 2080 816 1904 816 WIRE -608 864 -608 816 FLAG -608 864 0 FLAG 992 144 tank- FLAG 1424 144 tank+ FLAG 1120 224 ct FLAG 1248 624 M1-drive FLAG 752 544 M2-drive FLAG 176 608 N-FET-M3_drive FLAG 112 -16 P-FET_drive FLAG 2000 528 Out FLAG -80 -208 +12V SYMBOL ind2 1072 160 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value 0.220m SYMATTR Type ind SYMATTR SpiceLine Rser=0.022 Cpar=38p SYMBOL ind2 1248 160 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L2 SYMATTR Value 0.220m SYMATTR Type ind SYMATTR SpiceLine Rser=0.022 Cpar=38p SYMBOL nmos 1424 544 R0 WINDOW 0 -49 26 Left 2 WINDOW 3 -80 114 Left 2 SYMATTR InstName M1 SYMATTR Value AP9465GEM SYMBOL nmos 896 464 R0 SYMATTR InstName M2 SYMATTR Value AP9465GEM SYMBOL voltage -608 352 R0 WINDOW 123 0 0 Left 2 WINDOW 39 24 132 Left 2 SYMATTR SpiceLine Rser=1 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL pmos 272 64 M180 SYMATTR InstName M4 SYMATTR Value FDS4435A SYMBOL voltage 496 656 R0 WINDOW 3 -4 202 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 9 11.5u 0.02u 0.02u 11.35u 23u 5000) SYMATTR InstName V2 SYMBOL voltage 768 656 R0 WINDOW 3 -8 234 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 9 0u 0.02u 0.02u 11.35u 23u 5000) SYMATTR InstName V3 SYMBOL voltage -288 656 R0 WINDOW 3 -37 200 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(12 0 2.25u 0.02u 0.0.2u 6.9u 11.5u 10000) SYMATTR InstName V5 SYMBOL res -32 -32 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 47 SYMBOL ind2 1696 272 R180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName L3 SYMATTR Value 642m SYMATTR Type ind SYMATTR SpiceLine Rser=64.5 Cpar=10p SYMBOL res 2064 640 R0 SYMATTR InstName R6 SYMATTR Value 3300k SYMBOL res 2064 208 R0 SYMATTR InstName R7 SYMATTR Value 2.2k SYMBOL cap 1888 672 R0 SYMATTR InstName C2 SYMATTR Value 10n SYMATTR SpiceLine V=3k SYMBOL ind 2064 336 R0 SYMATTR InstName L13 SYMATTR Value 47m SYMATTR SpiceLine Rser=52 Cpar=37.5p SYMBOL cap 1792 -96 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 10n SYMBOL diode 1968 -96 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D1 SYMBOL cap 1936 192 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C4 SYMATTR Value 10n SYMBOL diode 1808 32 R0 SYMATTR InstName D2 SYMBOL cap 1216 288 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 3.3n SYMBOL res 1152 608 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 47 SYMBOL res 672 528 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 47 SYMBOL ind 848 208 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L4 SYMATTR Value 1m SYMATTR SpiceLine Rser=1.8 Cpar=63p SYMBOL FerriteBead 672 224 R270 WINDOW 0 16 0 VTop 2 SYMATTR InstName L5

SYMATTR SpiceLine Ipk=1 Rser=0.3 Rpar=587 Cpar=1.216p mfg="Wurth Elektronik eiSos" pn="742 792 18" SYMBOL FerriteBead 1680 64 R0 SYMATTR InstName L6

SYMATTR SpiceLine Ipk=1 Rser=0.3 Rpar=587 Cpar=1.216p mfg="Wurth Elektronik eiSos" pn="742 792 18" SYMBOL FerriteBead -544 -208 R270 WINDOW 0 16 0 VTop 2 SYMATTR InstName L7

SYMATTR SpiceLine Ipk=1 Rser=0.3 Rpar=587 Cpar=1.216p mfg="Wurth Elektronik eiSos" pn="742 792 18" SYMBOL cap -400 -144 R0 SYMATTR InstName C5 SYMATTR Value 100n SYMBOL nmos 272 528 R0 SYMATTR InstName M3 SYMATTR Value FDS6680A SYMBOL res 64 592 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 47 SYMBOL voltage -160 640 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 -170 247 Left 2 SYMATTR Value PULSE(0 5 9.73u 0.02u 0.02u 3.8u 11.5u 10000) SYMATTR InstName V4 SYMBOL FerriteBead 320 -128 R0 SYMATTR InstName L8

SYMATTR SpiceLine Ipk=1 Rser=0.3 Rpar=587 Cpar=1.216p mfg="Wurth Elektronik eiSos" pn="742 792 18" TEXT -328 992 Left 2 !.tran 0 100m 0 10n TEXT -336 928 Left 2 !.ic I(L4)=0.08 I(L3)=-0.00003 I(l6)=0.0 I(L1) =0 I(L2)=0.08\n.ic V(tank-)=3 V(ct)=1.5 V(tank+)=0 V(Out)=-1140 TEXT -328 1040 Left 2 !K1 L1 L2 L3 0.99

The idea is that a real circuit would be run with MOS-FET drive timings gen erated by a programmable logic device clocked by a VCO - probably the VCO i n a 74HCT4046 - whose operating frequency would be continuously (and automa tically) trimmed to match the actual resonant frequency of the device).

The 74HCT4046 has a guaranteed minimum operating frequency of 11MHz with th e control voltage at Vcc/2, so I'd design for a nominally 6.7MHz clock, giv ing me the 150nsec break-before make intervals I've put into the simulation as single clock periods. In reality, I might be able to get closer to 11MH z, and some programmable logic devices offer rather faster built-in VCOs.

My 23usec period is then 154 clock cycles, and the pulse width modulation o n the input to L4 can vary from 0/77 to 77/77, though the need to put in br eak-before make gaps makes the last step a big one - from 75/77 to 77/77.

Output voltage control is fairly coarse - 75 25V steps up to about 1850V an d a 50V step up to 1900V. One could feed an analog voltage into a monostabl e - running from say 50nsec to 200nsec - to add a finer control if it was desired, or one could just find (or make) a faster VCO and clock the system faster

The idea would be to have the "high" period of the PWM driving waveform lin ed up the middle of the peak voltage at the centre tap (V(ct) on the simula tion).

With the load simulated, the voltage at the centre tap rises rapidly for th e first 2sec of the cycle, flattens off for the next 5usec, starts falling

7usec after the start of cycle, gets halfway back down to 0V at 9usec and h its 0V at 11usec (give or take a bit of ripple).

My thought would be that if the desired voltage is n/77 of 1900V, the initi al 0V period would be some (77-n)/4 clock periods long. In the simulation, n=60, and if I'd done that the P-channel FET would turn on about 0.6usec into the cycle.

In fact it turns on a lot later at 2.25usec, which reflects a quite a bit o f mindless tinkering. I can't be bothered to adjust it back to a more sensi ble place - it's not going to make much difference

If the clock were slower than 6.7MHz, the V(ct) voltage would still hit 0V after 11usec and stick at about -0.4V until the start of the next cycle.

The timing control loop would probably look at the trailing edge of V(ct)at two points - at around 60 clock edges into the cycle and around 72 clock i nto the cycle - and adjust the VCO frequency so that V(ct) would hit zero a t 77 clock edges.

There's no point in getting too excited about the fine detail until I get around to building a real circuit - the simulated ripple is likely to be wo rse than the real ripple, because both skin effect and the finite conductiv ity of the ferrite core are likely to kill the ripple quite a lot faster th an it dies away in the simulation. And there's very little chance that I'll ever build a real version of the circuit, unless a potential customer emer ges from the wood-work.

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Bill Sloman, Sydney
Reply to
Bill Sloman
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Sorry, I do not have Ltspice but am I right in thinking the circuit is something like a buck converter current feeding a push-pull converter?

The phrase "break-before-make" switching leapt up at me - you definitely need that in the buck pre-convertor stage but in the push-pull stage (if it is what I infer from your description) then surely the mosfets need an overlapping make-before-break drive else the current feed inductor flyback will be uncontrolled?

Reply to
piglet

No. It's a Baxandall Class-D oscillator being feed from a pulse-width modul ated source. There's a discussion of the basic circuit on my web-site

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r1.htm

which includes a link to Peter Baxandall's 1959 paper (which happens to be difficult to get hold of - it came out in a special issue of the journal o f the (British) Institute of Electrical Engineers which hardly anybody subs cribed to).

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The voltage step-up all takes place in the oscillator transformer, after th e push-pull resonant converter. So I'm PWM-ing 12V down to something less, then using a step-up transformer and a voltage doubler to boost that lesser voltage by a constant factor of about 160.

The switches involved all get driven from the 12V supply.

Get LTSpice. It's free, good and very useful. It is likely to make you desi gn in more Linear Technology parts than you might it you were using some ot her clone of Berkely Spice, but that's not necessarily a bad thing.

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Bill Sloman, Sydney
Reply to
Bill Sloman

Thanks for the tip, I now have Ltspice and see the circuit. I can see how regulation occurs in the buck pre-convertor and the push-pull operates at a fixed rate.

What I meant was that if there is any dead-time when neither M1 nor M2 are conducting then the current in L4 will have nowhere to go{* see below] and the node L4-L1-L2 will fly up to an unknown, possibly dangerous level. The cure is overlapping drive to M1 - M2 but that will dampen the resonant action of C1 and create current peaks in M1-M2 - I wonder if one couldn't omit C1 and use the reflected capacitance of C3/C4? Then the switching action of D1 and D2 isolates M1/2 from handling current peaks and they [D1 and D2] can commutate silently during the crossover time - should make for very quiet operation.

If all you are doing with the wave is rectifying it why create a very low distortion sine wave? Is the main aim to get a low noise HV output?

[*] as I wrote this it occurred to me that perhaps the intention is that L4 "dries out" and there is no current flow when M1-2 changeover in which case a non-overlapping drive for M1-2 is OK. But if that is the case then why is there no voltage smoothing filter capacitance from the cold end of L4 to OV?

Thanks for the original paper, looks interesting.

Reply to
piglet

There's always the stray capacitance of the windings. I have kept the dead-time pretty low - if you don't the voltage at the centre tap does tend to fly away, but - if necessary - you could tame that with a 20V zener in this circuit.

As I put in my original post - yesterday (there are earlier threads on the same subject) you get ringing from the leakage inductance of the transformer, and making C1 a couple of nanofarads tames the amplitude and slows it down a bit.

As with all resonant converters, the main interest is being able to switch at close to zero current, largely eliminating the switching losses in M1 and M2.

Not really.

It takes a bit of reading, but it's well worth the effort. Jim Williams's Linear Technology application notes are also useful.

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Bill Sloman, Sydney
Reply to
Bill Sloman

Can't resist it.. Does one use imaginary components to build that imaginary power supply?

Reply to
Robert Baer

Nah, just real inductors and real capacitors...

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Thanks, 
Fred.
Reply to
Fred Bartoli

?

Not really. The transformer has been designed in some detail and the second ary winding needs 0.5mm of insulation (probably four layers of 120 micron t hick Mylar transformer tape) between each layer. If I could get a two secti on former, and bank the secondary, I could do better, but while I can imagi ne a two-section former for the ferrite core I've got in mind, I haven't be en able to find one at any of the broad-line distributors I've looked at.

It may be an imaginary part at the moment, but it has been imagined in some detail.

The rest of the inductors are off the shelf parts - L4 and L13 are big and tolerably expensive wound parts from the Farnell catalogue, and the rest ar e Wurth ferrite beads.

I've not done a detailed design for the digital bits that generate the timi ng waveforms, or the analog sampler that controls the VCO frequency to matc h the timing to the actual inductances of the transformer, but that part is pretty straightforward.

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Bill Sloman, Sydney
Reply to
Bill Sloman

Ever see those Hamamatsu PMT supplies built into the tube socket? Rather than a 1.2KV supply and resistor divider chain, they use a ~200v supply and a ten-stage voltage multiplier to supply all the electrodes. Find pdf on Hamamatsu HC123-01

Reply to
Bill Beaty

than a 1.2KV supply and resistor divider chain, they use a ~200v supply an d a ten-stage voltage multiplier to supply all the electrodes. Find pdf on Hamamatsu HC123-01

Sure. They have been mentioned before in the predecessors to this particula r thread. As I said then I like to run the photocathode to first dynode vol tage at the maximum allowed voltage - it helps the gain statistics and the transit time - and to set the last dynode at fixed voltage (since this volt age doesn't affect the gain of the tube, and tends to change with anode cur rent if you don't stabilise it, producing an output dependent change in gai n which can sometimes be inconvenient).

You could do both with a Cockroft-Walton multiplier set-up but it adds even more components to an already cramped area (and you've got fun getting the voltage clearances for voltages approaching 1.2kV (or 1.8kV for the last t ube I used).

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Bill Sloman, Sydney
Reply to
Bill Sloman

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