AD698 and fixed output

You've got a single supply set-up, yet image 106 shows the exciting waveform swinging between +5V and -5V.

It doesn't look as if you are paying proper attention to common mode ranges.

In particular, the output from the secondary winding (actually opposed secondaries) will be AC coupled to the driving waveform. If you - or somebody else - has grounded the centre-tap of the secondary, the voltages being fed into the +Ain and -Ain inputs will spend half their time below the negative supply rail, which will royally screw up the operation of the AD698 as a whole - charge carriers injected by via the substrate diodes tend to end up in unpredictable areas of the circuit and can have surprising effects.

Your circuit diagram for this area duplicates the data sheet circuit diagram for single supply operation, which relies on a 1M resistor to bias floating secondaries into a safe operating area, but it doesn't explicitly show the LVDT connections, which might - for instance - ground the centre tap of the opposed secondaries to a grounded shield (which is what I've done in the past).

Looking at the outputs of the secondies at +Ain and -Ain with a DC- coupled scope probe - or even a multimeter to get the actual average DC level - might be worht the trouble.

Something like this would explain why the A-demodulator output (image

-- Bill sloman, Nijmegen

Il 13/10/2011 12:16, Bill Sloman ha scritto:

Yep, 106 and 107 are the same waveform with oscilloscope set in AC and DC mode. I put also the AC one so you can read the measurement.

No. The centre-tap is disconnected.

In fact you see from image 108 that the output sine wave has a dc offset, so it doens't go below the supply rail.

I double checked the connections and seems ok.

I'm sorry, I don't understand what you're suggesting here.

Thank you, Bill Marco

I can't see anything about absolute voltage levels in image 108. There's absolute no zero reference anywhere on the screen. There are two unidentified arrow markers on the right and left sides of the image. You appear to be telling me that the left hand arow is the 0V marker and the right-hand marker the DC offset. What does the "CH1 /

You want to make sure of the absolute DC voltage range actually being applied to the +Ain input and the -Ain input.

I can see what the 1M resistor ought to be doing, but it would be nice to be sure that it is doing what it presumably did back in the Analog Devices application lab.

-- Bill Sloman, Nijmegen

Il 13/10/2011 18:35, Bill Sloman ha scritto:

The left arrow is the zero reference, that is at the middle of the vertical axis. 5V per division, so the dc offset is slightly over 5V.

So the sine wave is a nice 5.5 kHz of about 9.6Vpk-pk and about 5V dc offset.

The right arrow set the trigger value (5,60V falling edge). Is the standard simbology of Tektronix TDS series.

I apologize if I didn't explain that before.

Ok I got it. Wait a minute and I'll check that :)

. . . .

At maximum displacement:

-Ain dc offset: about 5.50 V

Here the two signals:

-Ain

The second one goes 0.7V below supply rail. Moving the lvdt the amplitude of the sine wave goes towards zero but the lowest side of the wave is still slightly negative.

This may clarify something?

Marco

Sure does.The second waveform is going 0.7V below the negative supply rail of your AD698 - which is to say it is turning the inevitable substrate diode on that input, and inject charge carriers into the silicon substrate for the whole circuit.

When this happens, it stops the circuit working the way it was designed to, because the charge carriers end up in odd places all over the circuit.

The scope says that the signals have RMS values of 6.44V and 5.9V respectively.

The AD698 data sheet sets an upper limit of 3.5V rms on the A and B signal inputs. You are over-driving the inputs. Unsurprisingly, the chip isn't reacting as it would to within-specification inputs.

This should be easy to fix, but you may need to replace the AD698 chip once you've re-engineered the signal levels down to values that the chip can handle.

-- Bill Sloman, Nijmegen

Il 13/10/2011 22:55, Bill Sloman ha scritto:

My fault was to calculate the rms value of the sine wave without considering the dc offset! That's why I set the oscilloscope in AC mode! I thought the chip will handle the common mode because the excitation sine wave is centered at vsupply / 2 regardless its own amplitude.

I hope my AD698 is still alive beacuse I don't have another in my drawer!

I've just replaced the R1 (R14 in my sch) with a 10k. Now the sine wave has a lower amplitude but the rms value is still over 12V because it has a Vsupply / 2 offset, as I said before.

I cannot reach a 3.5V rms on Binput in this way! I have the divider on-board, but it shouldn't be used unless you want to overdrive the lvdt.

Thank you again! You're helping me a lot to understand this circuit.

Marco

The sine wave driving the primary of the LVDT is going to be centred at Vsupply/2, and won't give you any problems.

The sine wave coming out of the - galvanically isolated - secondaries can be bigger (have a higher peak-peak-to-peak voltage swing) than the excitation waveform going into the primary, and it's DC offset depends on what you've done with the secondary connections.

If you tied the centre-tap of the secondaries to Vsupply/2 you'd at least know what was going on.

The Analog Devices single supply example circuit just relies on a 1M resistor to ground to set up the DC conditions. If you overdrive the

All rather depressingly messy.

The primary excitation voltage doesn't matter, of it itself. What's important is the maximum voltage difference that it sets up across the LVDT secondaries and thus the +/-Ain inputs. This seems to be too high

- high enough to drive (or have driven) the A inputs into avalanche breakdown at some point, which is presumably why one of the A inputs is now swinging below 0v to collect enough charge to make up for that being driven into the ADS698 chip on a positive peak.

Not enough ...

-- Bill Sloman, Nijmegen

Il 14/10/2011 12:19, Bill Sloman ha scritto:

It's directly connected to Binputs! So it is *always* greater than 3.5V rms.

At the moment the problem is still on the primary: the excitation voltage is applied to Binputs and it doesn't respect the specifications.

Ok.

I will try to reduce again the excitation voltage (and thus the secondary one).

The last thing I'm asking to explain me is why you don't mind the Binputs voltage range.

Marco

ms.

Not according to the data sheet. That does warn (on page 7) you that if you set up the AC content of the excitation voltage to be higher than 3.5V rms, you do have to use a voltage divider to present a lower voltage to the B inputs.

It's obviously got to be limited - just like the signal going into the A inputs (as it says on page 2 of the data sheet) - but the outputs are coming from the chip itself, and the data sheet has told you that you have to limit the AC content of the signal hititng the B inputs to less than 3.5V rms, so I was figuring that since you did read the datat sheet, you wouldn't have forgotten to take this into account.

-- Bill Sloman, Nijmegen

Il 14/10/2011 16:37, Bill Sloman ha scritto:

Sorry, we'are talking about different things. I say:

Anyway, I'm going to setup the divider to achieve the correct input voltage. Let's see what happens.

Bye Marco

ms.

Not according to the data sheet. That does warn (on page 7) you that if you set up the AC content of the excitation voltage to be higher than 3.5V rms, you do have to use a voltage divider to present a lower voltage to the B inputs.

It's obviously got to be limited - just like the signal going into the A inputs (as it says on page 2 of the data sheet) - but the outputs are coming from the chip itself, and the data sheet has told you that you have to limit the AC content of the signal hititng the B inputs to less than 3.5V rms, so I was figuring that since you did read the datat sheet, you wouldn't have forgotten to take this into account.

-- Bill Sloman, Nijmegen

The Analog Devices data sheet is remiss in defining the maximum signal input the A and B inputs can survive in terms of an "rms voltage".

If you sum the squares of the successive DC voltages coming out of the excitation pins (exc1 and exc2)and take the square root of the sum over a full cycle it does have to be more than 3.5V. This is obviously not what Analog Devices have in mind - they presumably expect you to understand the RMS voltage to be the sum of the squares of the differences between the output voltages and the Vs/2 DC offset.

This isn't mathematically necessary, but if you were to take the attitude that an rms voltage specification is only useful or necessary for an AC waveform, then you might then expect your customers to understand the rms voltage specification as a limitation on the AC component of the waveform.

I'd have been much happier if they'd specified the limitations of the A and B inputs in terms of the maximum voltage difference between these inputs - but maybe there's a thermal limit somewhere inside the chip.

ge.

I look forward to hearing how it turns out.

-- Bill Sloman, Nijmegen

Il 14/10/2011 21:52, Bill Sloman ha scritto:

Bill,

I tried with the voltage divider but it just reduced the amplitude of all signals.

However, I'm close to solve the problem thanks a hint read on a forum. The A input should be polarized at Vs / 2 too. In fact, adding another

Now I see two dc voltages at both A and B filter output. The A filter slightly changes with lvdt displacement.

This variation is very small: about 150 mV. I measured the phase difference between the primary and secondary of the lvdt and I found it's about 5.4°.

I think the synchronous demodulator is not working because it has a shifted reference signal. Unfortunately I can't add the lead/lag compensation network on my PCB.

So I'm going to mount the whole front-end on a prototype board to verify if compensating the phase difference leads the AD698 to work properly.

I thank you very much for your patience. Marco

You'd be better off connecting the centre-tap of the LVDT secondaries to Vs/2. A resistive divider would do it, and my guess is that two 100k's would give you an adequate bias impedance.

This shouldn't matter; it attenuates the output by the cosine of 5.4=B0

- 0.996.

It's more likely that it isn't working because you blew it up by putting excessive voltage differences between the A+/A- and B+/B- inputs.

A couple of degrees of phase shift won't make very much difference.

It won't make much difference - 5.4=B0 is almost negligible.

-- Bill Sloman, Nijmegen

Il 17/10/2011 18:39, Bill Sloman ha scritto:

Solved. You're right about the phase difference, it doens't matter.

The problem of the small output change was related to the signal reference voltage. It was too low. With single supply it's not possible to achieve a 0-5V output. The ds characterize the voltage range only for dual-supply but using the lower rail and 0V you can see the swing limits.

Raising the signal reference voltage to Vs / 2 provides full swing. Now I have to find the best values to fit my application but fortunately the AD698 didn't blow up!

Bye Marco

Congratulations! I'm glad to hear that the AD698 didn't blow up.

The section of the AD698 data sheet that discusses setting the signal reference voltage for single supply applications - on page 8 - isn't easy to follow, and (crucially) lacks any discussion of why you need to get the voltage right, and what goes wrong if you don't.

Now we know. It seems to have taken a week to work out.

-- Bill Sloman, Nijmegen