A stupid post about Intel's latest computer chip ( s)

"Stack dancing" is a kinder equivalent.

Jerry

Words like DUP, SWAP, DROP sprinkled in the source.

Followups set to comp.lang.forth

- anton

Ohh Good grief, don't you know every Intel Mac is going to ship with an Array Async Chip for the Openboot application! Only Joking, but who knows what will happen.

Also, notice that the company name for Chuck's chip is now, INTELasys (capitalisation mine)!

Going where no gamer has gone before ... super scalable multiple parallel symetric parallel processors ( with LEGO(tm) like expandability,) executing multi layered sprites and partion trees to drive more ultra hi resolution projection panels, and, so blindingly fast , a super computer beyond which no mere mortal could hope to survive.

Oh, well, national security administration and big business rule.

Or, whether asychronous or syschronous is your game, name this tune, in the least number of notes,

URL,

I believe the programmable multiplexer nodes ( the non-diagonal, ie not the "enhanced stack machine" nodes along the diagonal) maybe the least transistors for the greatest multiplexing efficiency.

Anyone else believe in eternity?

Forth doesn't run as an interpreter. What is sometimes called the "inner interpreter" is a VM that compiled code runs on. That's absent in a native-code implementation because there is no virtual machine. The "outer interpreter" looks up source commands and executes them. If the commands are to compile a new word, then that's what it does. The only real interpreter in any Forth includes the compiler.

Jerry

Just fine? SPARC *always* passes the return address in a register and has for approx. 20 years. No problems with recursion there. And you never need to explicitely save the return addresses you've collected on the stack either.

Casper

All Forths need a text interpreter for the interactive use of the language. Modern Forths tend to generate executable code as machine code. Older Forths or Forths for some 8/16 bit CPUs have used lists of addresses (threaded code).

Our VFX Forth for Windows is an example of a modern native code Forth compiler with good optimisation. The evaluation version is available as a free ownload from our website.

Stephen

A script. ;-)

Cheers! Rich

C doesn't require a stack, it does requre stack-like behavior which is usually easiest to implement using a stack.

ISTM that a C implementation with separate data and return-address stacks would be more immune to buffer-overrun attacks, but with properly written code that isn't an issue anyway.

Bye. Jasen

yeah? how would recursion work?

if the top end of the stacks are stored in special processor registers that needn't be.

I've heard of forth implementations that run in machine code - define something and the definition is stored as machine code that executes the operations in the definition. would that be a compiler, or is it still an interpreter?

Bye. Jasen

OK, I'll bite. I see post and reposts of this incoherent blather going back

Suppose I wanted to build a system based on this chip, where do I buy them, how much do they cost?

Who fabricates them now, today?

Where can I buy a single-processor development kit?

What is the power consumption?

Where are the performance specifications and timing diagrams?

How is it interfaced to memory?

What are power supply and voltage requirements?

What are the pinouts?

Where's the data sheet?

What compilers are available for it?

Who makes them?

Who publishes new words and vocabularies for it?

How is it debugged?

What about realtime applications?

Interrupt services?

If it isn't real, now, here, today, when will it be made real?

Where are the VHDL or other sources for modeling and fabricating these devices?

What is the web site of the fabricator and how many samples have they made?

Who are your customers and what systems have they produced based on this design?

Path: g2news1.google.com!news3.google.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!trnddc03.POSTED!befad20c!not-for-mail From: Geoff Newsgroups: comp.lang.java.machine,comp.arch,comp.lang.forth,sci.math,sci.electronics.design Subject: Re: A stupid post about Intel's latest computer chip ( s) Message-ID: References:

X-Newsreader: Forte Agent 3.1/32.783 X-No-Archive: yes MIME-Versi>

OK, I'll bite. I see post and reposts of this incoherent blather going back

Suppose I wanted to build a system based on this chip, where do I buy them, how much do they cost?

Who fabricates them now, today?

Where can I buy a single-processor development kit?

What is the power consumption?

Where are the performance specifications and timing diagrams?

How is it interfaced to memory?

What are power supply and voltage requirements?

What are the pinouts?

Where's the data sheet?

What compilers are available for it?

Who makes them?

Who publishes new words and vocabularies for it?

How is it debugged?

What about realtime applications?

Interrupt services?

If it isn't real, now, here, today, when will it be made real?

Where are the VHDL or other sources for modeling and fabricating these devices?

What is the web site of the fabricator and how many samples have they made?

Who are your customers and what systems have they produced based on this design?

Please deacronymize. This is plainly rude.

Although some people consider a spam bot totally inappropriate, I for one, enjoy an occasional curve ball; however, label from /bot-xyz/, appropriately, maybe, in my view.

HO HO HE HE , thanks for the nice things said , in a twist of words sort of way, but I got to go to bed , The news tonight talks about a deer that jumped into the front seat of a womans vehicle, an eight point buck in Farmington Minnesota, ... but I got protypes to layout for operating laser cutter mill, special setups, NC macro tool building fun, 1/3 my previous earnings, no health, etc. ( no way!), but anyway.

.... What /was/ your clearance? FBI, surely not CIA or NSA, plus close ties with coporate? I don't need this s*it anymore!

Path: g2news1.google.com!news4.google.com!news3.google.com!border1.nntp.dca.giganews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!cyclone1.gnilink.net!spamkiller.gnilink.net!gnilink.net!trnddc02.POSTED!befad20c!not-for-mail From: Geoff Newsgroups: comp.lang.java.machine,comp.arch,comp.lang.forth,sci.math,sci.electronics.design Subject: Re: A stupid post about Intel's latest computer chip ( s) Message-ID: References:

X-Newsreader: Forte Agent 3.1/32.783 X-No-Archive: yes MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 83 Date: Mon, 31 Oct 2005 00:22:11 GMT NNTP-Posting-Host: 71.104.149.134 X-Complaints-To: snipped-for-privacy@verizon.net X-Trace: trnddc02 1130718131 71.104.149.134 (Sun, 30 Oct 2005 19:22:11 EST) NNTP-Posting-Date: Sun, 30 Oct 2005 19:22:11 EST

A Forth processor document in the comp.lang.java.machine newsgroup. Telling.

Even more telling.

"SUMMARY: I am an experienced programmer. Also, I define a high gross value for one dollar. "

Whatever that means.

For those who have not already found the origin of Mark's perpetual reposts of HTML-ified quoted gobbledygook, here is the link to decently formatted descriptions of the x18 and other stack processors and Chuck Moore's original work. (Apparently.)

And the 25X:

The content of Mark's posts can be found here, properly formatted and readable.

I call the reader's attention to opcode 14. Called "or" it is documented as "Exclusive-or S to T". Is it OR or XOR? If XOR, where is the OR instruction? If it is OR then lacking XOR the processor would not lend itself to modern day cryptography or graphics processing where 2400 Mips would prove itself useful. Of course it's always necessary to have the all-important NOP instruction in a 2400 Mips processor (instruction 1E). We can do "nothing" really, really fast. Why aren't OR, AND and XOR all implemented in this processor and the NOP discarded? Why is a NOP instruction even included in a processor of this type or any modern HLL such as Forth? Surely we aren't doing timing loops with NOP instructions in the 21st century. How would a NOP instruction benefit the design of a processor that has no clock? I am no Forth programmer, but it seems strange to claim "27 instructions ideally suited to Forth" where XOR is a primitive word, but to have no hardware instruction for it. I would also point out that 2^5 is 32 and the Moore document is 5 opcodes short of a full deck. The following opcodes are not documented in the Moore description of the x18 core:

I repeat and amplify my question: Where is the source code to the X18 and the 25x?

It would also appear that even Chuck Moore has given up on the 25x:

The Forth primitive words:

The Forth instruction frequencies of occurrence:

The b16 processor was more completely and accurately documented and it has XOR, COMpliment, AND, OR and two NOP instructions.

Mark, you sound like a really smart and zealous guy, who has determined he has a mission to realize a stack processor design and bring it before the world. Your 1999 resumé would _not_ get you a job working for me. Nevertheless, if you somehow ended up working for me I would keep you as far as possible from my customers, preferably sequestered in a lab or a cubicle where you could work on projects that could be transferred to and realized by a design team who knows how to document IP and write decently so others can understand the final product. I would not trust code written by you unless I could see for myself how well commented and implemented it was, your written work is sloppy and incomplete though voluminous. I expect your code is the same.

An obvious strawman for some idiotic C v.s all contenders flame/war, ( A "spam bot" robotic hook, is another, guess )

An obvious strawman for some idiotic C v.s all contenders flame/war, ( A "spam bot" robotic hook, is another, guess )

A Forth processor document in the comp.lang.java.machine newsgroup. Telling.

Even more telling.

"SUMMARY: I am an experienced programmer. Also, I define a high gross value for one dollar. "

Whatever that means.

For those who have not already found the origin of Mark's perpetual reposts of HTML-ified quoted gobbledygook, here is the link to decently formatted descriptions of the x18 and other stack processors and Chuck Moore's original work. (Apparently.)

And the 25X:

The content of Mark's posts can be found here, properly formatted and readable.

I call the reader's attention to opcode 14. Called "or" it is documented as "Exclusive-or S to T". Is it OR or XOR? If XOR, where is the OR instruction? If it is OR then lacking XOR the processor would not lend itself to modern day cryptography or graphics processing where 2400 Mips would prove itself useful. Of course it's always necessary to have the all-important NOP instruction in a 2400 Mips processor (instruction 1E). We can do "nothing" really, really fast. Why aren't OR, AND and XOR all implemented in this processor and the NOP discarded? Why is a NOP instruction even included in a processor of this type or any modern HLL such as Forth? Surely we aren't doing timing loops with NOP instructions in the 21st century. How would a NOP instruction benefit the design of a processor that has no clock? I am no Forth programmer, but it seems strange to claim "27 instructions ideally suited to Forth" where XOR is a primitive word, but to have no hardware instruction for it. I would also point out that 2^5 is 32 and the Moore document is 5 opcodes short of a full deck. The following opcodes are not documented in the Moore description of the x18 core:

I repeat and amplify my question: Where is the source code to the X18 and the 25x?

It would also appear that even Chuck Moore has given up on the 25x:

The Forth primitive words:

The Forth instruction frequencies of occurrence:

The b16 processor was more completely and accurately documented and it has XOR, COMpliment, AND, OR and two NOP instructions.

Mark, you sound like a really smart and zealous guy, who has determined he has a mission to realize a stack processor design and bring it before the world. Your 1999 resumé would _not_ get you a job working for me. Nevertheless, if you somehow ended up working for me I would keep you as far as possible from my customers, preferably sequestered in a lab or a cubicle where you could work on projects that could be transferred to and realized by a design team who knows how to document IP and write decently so others can understand the final product. I would not trust code written by you unless I could see for myself how well commented and implemented it was, your written work is sloppy and incomplete though voluminous. I expect your code is the same.