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Thank you all for the advice and entertainment. This place as a certain neighborhood bar feeling about it.

--
When was the last time you posted a schematic?

The rest of us do rather regularly, while all you do is sit around,
bitch and moan, and live in the past.


JF

Right. It's not "work" Slowman's a piece of.

I read "regulated +12V", and the 9-14V as a signal of some sort.

Is Slowman so dumb-shit ignorant that he thinks I would reference on something moving?

...Jim Thompson

--
| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
 I love to cook with wine     Sometimes I even put it in the food

well, thank you all again...last call

He did post a simulation of a rather weird version of a Baxandall resonant oscillator. Barbaric newbie biasing. And he didn't understand why it didn't squegg in simulation.

Better than nothing, I suppose.

John

But then again. neither does John, on the evidence available.

Since it's worth nothing to anybody else, there's not a lot of motivation.

I've spent some time (and a little money) trying to find Peter Baxandall's original paper, on "Class-D oscillators",

Baxandall, P.J, Proc I.E.E 106, B, 748 (1959)

without any success. My little brother (who has convenient accesss to university libraries that ought to have copies of the journal) reports " it wasn't in their complete 1959 Part B collection. From some checking of citations, I've worked out it is in a supplement of presumably the May 1959 Part B issue."

The late Tony Williams, who was the source of the reference, isn't available for advice.

-- Bill Sloman, Nijmegen

Of course I know why it doesn't squegg. Squegging requires a squegging-frequency modulator/demodulator loop with the usual oscillation criteria, namely gain >1 at 0 degrees phase shift around the loop. The classic tube and transistor oscillators often had such properties; your circuit doesn't.

Super-regenerators, the ultimate squegg machines, were often 3rd or

4th order feedback loops. The modulator/demodulator loop involved a high-Q resonator; the demodulator (tube grid or b-e junction, rectifying the rf signal and reducing device bias hence transconductance) usually had its own RC time constant; and there was usually a bypassed cathode/emitter resistor. Sometimes even a fourth pole, a supply inductor or signal output transformer winding.

Control theory. You're self-declared to be an expert here.

John

On 19 feb, 02:34, John Fields wrote:

Version 4 SHEET 1 880 680 WIRE 192 16 -288 16 WIRE 368 16 192 16 WIRE 192 64 192 16 WIRE 368 144 368 16 WIRE 192 160 192 144 WIRE 336 160 192 160 WIRE 544 176 400 176 WIRE -288 192 -288 16 WIRE -128 192 -288 192 WIRE 336 192 64 192 WIRE -288 256 -288 192 WIRE 192 272 192 160 WIRE 256 272 192 272 WIRE 400 272 336 272 WIRE 544 272 544 176 WIRE 544 272 480 272 WIRE -128 288 -176 288 WIRE 192 384 192 272 WIRE 416 384 192 384 WIRE 544 384 544 272 WIRE 544 384 480 384 WIRE 192 448 192 384 WIRE -288 560 -288 336 WIRE -176 560 -176 288 WIRE -176 560 -288 560 WIRE 192 560 192 528 WIRE 192 560 -176 560 WIRE 368 560 368 208 WIRE 368 560 192 560 WIRE -288 592 -288 560 FLAG -288 592 0 SYMBOL References\\\\LT1021-5 -32 240 R0 SYMATTR InstName U1 SYMBOL Opamps\\\\LT1006A 368 112 R0 SYMATTR InstName U2 SYMBOL voltage -288 240 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL res 176 48 R0 SYMATTR InstName R1 SYMATTR Value 10k SYMATTR SpiceLine tol=3D0,1 SYMBOL res 176 432 R0 SYMATTR InstName R2 SYMATTR Value 10k SYMATTR SpiceLine tol=3D0.1 SYMBOL res 496 256 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R3 SYMATTR Value 124k SYMATTR SpiceLine tol=3D0.1% SYMBOL res 352 256 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R4 SYMATTR Value 1k SYMATTR SpiceLine tol=3D1 SYMBOL cap 480 368 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C1 SYMATTR Value 0.1=B5

The LT1021-5 is a ridiculous over-kill for the application, but it is in the LTSpice library while the cheaper LM4040C50FTA I mentioned earlier isn't.

I've also left out the 100nF bypass capacitor that even the LT1006 single supply op amp should have.

Almost any other low off-set single supply op amp that could survive the peak supply voltage would do as well as the (elderly) LT1006.

I've followed Jim Thompson in figuring that the OP wants to digitise the supply voltage range from 10V (which would give 5V at the output of the LT1006 in this circuit) to 14V (which would give 0V at the output of the LT1006, if the LT1006 could pull right down to the 0V rail, which it can't, since it can only pull 40uA down to about 50mV).

The 0.1% resistors are E96 values and available ex-stock from Farnell, some of them as single parts (though for many you have to buy five at once, typically for more than a buck apiece).

-- Bill Sloman, Nijmegen

Except that the classic circuit does squegg in real life, if you make the inductor too big. The first one I ever built back on 1968 squegged continuously, until I took off a lot of the turns that that I'd tediously handwound onto the inductor.

Don't remember ever making that claim. I can tune a DPI control loop, but state-variable control theory and self-tuning control loops I've so far been able to palm off onto people who do think they have mastered control theory.

You seem to share their enthusiam for applying their expertise to situations that they didn't really comprehend.

-- Bill Sloman, Nijmegen

On 19 feb, 20:49, snipped-for-privacy@ieee.org wrote:

Version 4 SHEET 1 880 680 WIRE 192 16 -288 16 WIRE 368 16 192 16 WIRE 192 64 192 16 WIRE 368 144 368 16 WIRE 192 160 192 144 WIRE 336 160 192 160 WIRE 544 176 400 176 WIRE -288 192 -288 16 WIRE -128 192 -288 192 WIRE 336 192 64 192 WIRE -288 256 -288 192 WIRE 192 272 192 160 WIRE 256 272 192 272 WIRE 400 272 336 272 WIRE 544 272 544 176 WIRE 544 272 480 272 WIRE -128 288 -176 288 WIRE 192 384 192 272 WIRE 416 384 192 384 WIRE 544 384 544 272 WIRE 544 384 480 384 WIRE 192 448 192 384 WIRE -288 560 -288 336 WIRE -176 560 -176 288 WIRE -176 560 -288 560 WIRE 192 560 192 528 WIRE 192 560 -176 560 WIRE 368 560 368 208 WIRE 368 560 192 560 WIRE -288 592 -288 560 FLAG -288 592 0 SYMBOL References\\\\LT1021-5 -32 240 R0 SYMATTR InstName U1 SYMBOL Opamps\\\\LT1006A 368 112 R0 SYMATTR InstName U2 SYMBOL voltage -288 240 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL res 176 48 R0 SYMATTR InstName R1 SYMATTR Value 100k SYMATTR SpiceLine tol=3D0,1 SYMBOL res 176 432 R0 SYMATTR InstName R2 SYMATTR Value 100k SYMATTR SpiceLine tol=3D0.1 SYMBOL res 496 256 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R3 SYMATTR Value 124k SYMATTR SpiceLine tol=3D0.1% SYMBOL res 352 256 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R4 SYMATTR Value 1k SYMATTR SpiceLine tol=3D1 SYMBOL cap 480 368 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C1 SYMATTR Value 0.1=B5

Sorry about the typo in the LTSpice circuit diagram - not 10k resistors, but 100k resistors (corrected above).

The biggest soucre of uncertainy on the output is the tolerance on the voltage reference - the LM4040C50FTA offers +/-0.5% on 5V, or +/- 25mV, which shows up as +/-56.25mV on the output, equivalent to +/-45mV on the 10V to 14V range of the supply voltage to be digitised. The LT1021-5 would be a factor of ten better, but does cost about ten times as much (at around $10), and the contribution from the tolerances on the. 0.1% resistors would swamp that.

I know that your marketeers insists that you make these claims. What is actually going to be the difference between this one and all other the ones you've made the same claim about in the past?

Worse still, I'm frustrated. The last digitial delay generator for which I was responsible pre-dated the MC100E195.

I got to design one some ten years later where I could design it in and I worked out how I could cope with its nasty temperature sensitivity, but the potential customer ran out of graduate students before we could start building it, leaving me with a couple of hundred pages of A4 sheets of Orcad circuit design, and no evidence of how well it might have worked in practice.

Now Motorola are selling the MC100EP195, which would have let me get away with a 100MHz clock (though 500MHz crystal clocks were essentially off-the-shelf items, at a price, using chemically thinned crystals and offering sub-picosecond jitter).

--
Bill Sloman, Nijmegen

--
That\'s just ugly.

What the OP wants is:

        14V________
          /
    9V__ /_________
        /|
       / |
      /  |
Vin__/0V |
         |
         |
         |
         |
         |
         |
         |
         |5V________
         | /
Vout_____|/0V 
         |
         |
Or:      |
         |
Vout_____|5V
          \\
           \\_______0V
 

And, unless I\'ve done something dreadfully wrong, your circuit certainly
doesn\'t provide that.

Nor do you have a source which varies from 0 to 14 volts, and you
haven\'t even bothered to take the comma out of the tolerance spec for
R1.

Also, there\'s no run-time associated with the file, so did you even
bother to run it or did you just draw it and make a lot of assumptions?

JF

I have no "marketeers" and when anybody insists on anything in my company, it's me. Except when they order Hawaiian pizza, which is repulsive, and I an powerless to stop thaem.

Two differences: one can load a new set of delays and widths and queue them into the hardware, and they get loaded without trashing any delay cycles. Most DDGs abort the current timing cycle if you reprogram them, which can be bad news. Even better, one can pre-program a sequence of thousands of shots, and it will load a new set of timings every time it's triggered. This is cool for things like stroboscopic photography or radar target simulation. The idea of reprogramming a delay generator while it's being triggered at a high rate is inherently tricky.

Micrel has some ECL delay-line chips. 10 bit resolution and guaranteed monotonic. Better than the On stuff, and much cheaper.

Hmmm, yet another failure. You seem to have a lot of failure stories.

Not Motorola: OnSemi.

The ECL delay-line chips have nasty tempcos that change with programmed delay. And they are expensive power hogs. But they are true delay lines, storing multiple edges inside, so have their place.

The CMOS delay-line chips I've used are really bad.

John

In article , snipped-for-privacy@highTHISlandtechnology.com says...>

Have you looked at EC2 (Engineered Components Company)? I haven't used them in ~30 years but they had some 2-decade 10nS ECL delay lines that were reasonably good. I used tons of their one decade

10nS delay lines (the program got canceled before we needed many of the .1nS resolution parts).

[snip]

Aha! I remember those. Used them in a clock restorer, where the source could have "long" periods of missing transitions. Wrapped around some logic to make a phase "jerking" accurate oscillator.

...Jim Thompson

--
| James E.Thompson, P.E.                           |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
 I love to cook with wine     Sometimes I even put it in the food

We mostly make our own fine delays from capacitor ramps and comparators and dacs. That's cheap, has ps resolution, low jitter, low TC. A good analog ramp delay can have RMS jitter of 1 part in 50,000 of the total delay range. 1 ps RMS in a 50 ns ramp is do-able.

John