3 dB bandwidth

The document is Internal to the AEC. This is common for working documents within standards bodies.

I downloaded the courtesy copy and looked around the AEC pages. It appears to be a professional organization, but I don't see any ANSI, or other affiliation, which bothers me a lot.

However, the AEC is taking into account definitions used by some Standards bodies (but perhaps not all), and appears to NOT be setting new definitions, but providing *guidelines* for the AEC member organizations use of the expressions. Guidelines are NOT standards, so where's the problem except between the parts of the audio industry who do and do not belong to the AEC?

Don

Of course not. My wife would never allow such things.

By the RES body.

Don

I suggest that everyone take advantage of a free download of the RES document discussing the issue. It's only a few pages, and is interesting. The download is a type that you cannot print or save, but most of us know how to work with that.

Don

Aside from its contributions to the accepted standards bodies, the AES - not the atomic energy commision btw ;-) - publishes 'guides for recommended practice'.

This is in effect a statement of accepted ( and preferred ) usage.

Graham

The problem comes elsewhere in this thread, where "Pooh Bear" assured me that the documents did contain decibel standards: "Bell Labs definition is *not* the standard. ... The standard is set by the AES".

If, as he claims, he is an AES member with access to these documents, he should have been in a position to know whether or not his assertions were correct before he made them.

An honest mistake is usually followed by an apology.

Over to you "Pooh Bear".

My ( and industry practice ) usage of the decibel is *no mistake*.

Graham

Auger Electron Spectroscopy?[1] Atomic Energy Something?

Sorry.

M'Kay. ;-P

Cjeers! Rich

Yes, but then we tend to think more in relative power levels than voltages, anyway, especially when working with noise and intermodulation.

BTW, I *can* think of one absolutely unambiguous use of the dBm that requires no qualification at all, as to impedance.

Thanks, Win. Sorry for the delay in replying - I thought I had the mold toxins under control. But then the weather changed and I had to figure out where they were coming from and how to get rid of them.

Your suggestions are very good. It looks like floating the op amp supply and using an inverter at the input to the ADC solves the cmrr problem. Thanks!

I would like to allow much higher input voltages, perhaps up to +/-1kV. You have mentioned your 1100V amplifier several times before, but I haven't been able to find any circuits in google. I hope one day you might let us know how it works.

I tried stacking NPN's and PNP's in a complimentary emitter follower with a crossover reducing resistor between the bases and emitters. It looks like this may work. It could be extended to any desired voltage with very low power consumption and reasonable bandwidth.

One problem was trying to model it. The version of SPICE I use does not like having the op amp supply voltages track the input signal, and it gave very wierd output signals. I tried several op amps with similar results and finally found the UA741 barely works in this circuit. However, SPICE claims the system bandwidth is over 1MHz, which I do not believe at all.

As usual, one big problem is protecting the inputs. Using a pair of fets in series with the input to limit the current only works to 500V or so.

How do HP, Fluke and the others get above this limit?

Mike Monett

It turns out the problem was having the collector of one transistor feed the emitter of the next in the stack. Apparently SPICE doesn't like handling leakage currents in series. Adding a 1,000 megohm resistor across each transistor solved the problem, and the simulation now runs much better.

One thing I'll have to watch out for. Shorting the output to ground seems to saturate all the transistors in the stack except one. This now has the full supply voltage across it. It will blow, of course and probably short. This would place the full supply voltage across the remaining transistors, which would also likely blow. Like John says, it is probably a good idea to add some series resistance to limit the resulting shrapnel. With a low value of load resistance in place of a short, the stack seems to saturate in a peculiar manner. With three transistors in series, the one closest to the op amp saturates first, then the middle one. This leaves the ones connected to the supply voltage to handle the full load current. I'll have to ponder a while to figure out why they saturate in such a predictable sequence, but it seems to be real and not a SPICE artifact.

Mike Monett

According to spice, if the output is instantaneously shorted in my design the series MOSFET transistors nicely ** share the voltages, which is a natural outcome of their matched Coss capacitances in series. Each FET's operation is dominated by its Ciss, which holds its gate voltage steady just after the event. Each one continues to conduct at the same current, and they then progress together to another current and to the current limit.

Very encouraging. I originally intended to look at MOSFETs since they handle avalanche better than bipolar. But you mentioned elsewhere the high capacitance of MOSFETs limits the bandwidth, and series MOSFET's tend to oscillate in linear applications.

A simple calculation assuming 1 meg gate impedance and 1 nF lumped capacitance shows a -3dB point at 1 / (2 * pi * 1e6 * 1e-9) = 159 Hz, not including Miller effect. My bandwidth needs are modest, but this may be a bit low to settle in a reasonable time.

So I was looking at complimentary NPN/PNP's stacked in an emitter follower configuration. Bandwidth is much better, but SOA is definitely a problem with this approach.

What kind of bandwidth do you get with MOSFET's? Does the high gate resistance help stop the oscillations?

Mike Monett

Update on cascode MOSFET's:

I tried strings of 2, 3, and 4 NMOS and PMOS in series. In each case, they have a very severe turnon transient that doesn't seem to show up with bipolars. This can give a huge distortion at zero-crossings, with long recovery times.

Fiddling with the values for the crossover resistor and gate bias resistors helps, but bottom line is the gate bias string needs to be a much lower value than with bipolar.

This increases the power needed to handle +/-1kV. For example, bipolar was happy with less than 1 watt with good bandwidth, but mosfet's seem to want 20 watts or more. Even then, the system bandwidth is quite low (much less than 1KHz) before severe distortion sets in. This makes it difficult to get a figure for the settling time.

In the target application, the circuit was intended to provide a high-impedance buffer for DC, and perhaps low frequency AC. But the high input capacity of the mosfets means wasting a lot of power in the bias string, or putting up with very long settling times. The input capacitance is a killer, as you have mentioned previously.

So if you have found a way around this problem, no wonder you don't want to talk about it:)

Mike Monett

OK, I think I found the solution. Just drive the gates of the mosfets with complimentary bipolar. The bias string can be very low power and still give enough base current for the transistors to drive the input capacity of the mosfets.

I tried two NMOS and PMOS in series with one NPN/PNP driver for each pair. The improvement was dramatic. No turn-on transient was visible on the gates. It followed a 5KHz 1,900V p-p sine wave with a 50k || 50pF load with no problem.

This is at least a factor of 10X improvement in bandwidth with 10X less power wasted in the bias string. If you want to push it further, just increase the bias current. Of course, the bipolar string would need more transistors to handle the high voltage, but that's still cheap.

Next I need to investigate the short-circuit performance, but I have a feeling it will be OK.

Mike Monett

One finds much higher-voltage N-type FETs than P-types, so I've been using all NMOS strings, in a totem-pole push-pull circuit. With a Darlington BJT to drive it at the bottom, for higher transconductance and predictable Vbe.

I gather your setup is the common NMOS + PMOS follower circuit? If so, what PMOS parts are you using and what is their voltage rating? Also, how are you getting the 5KHz 1,900V p-p sine wave to drive the two NMOS and PMOS push-pull output with?

Are your measurements real, or *Ahem* Are they just spice measurements? If so, did you bench-vet your MOSFET's subthreshold model? The standard models are completely masssively defective, but in a way that makes the FET's transconductance appear to be very high at low currents, say under 100mA, which improperly wipes out much of their high Ciss problem, which can then make linear circuits appear to work much better than in real life.

Win,

Everything is in SPICE to evaluate different configurations. Parts selection comes later when I am pretty sure it will work. The basic configuration is the floating op amp driving an inverting stage as you suggested earlier.

So far the complimentary NPN/PNP bipolar follower has the best AC performance, but it is difficult to protect against overload. A plain NMOS/PMOS follower with multiple mosfets has extremely poor bandwidth and large turnon transients due to the high gate resistance. The resistance is across the supply voltage of 1KV, so a low value would waste power.

Driving the mosfet gates with complimentary bipolar followers seems to eliminate this problem. Adding small (30pF) caps across the bias resistors seems to allow much higher bias resistance and still keep good ac response.

I searched google groups and downloaded most of the threads on high voltage amplifiers, so I am familiar with your discussions about mosfet subthreshold characteristics.

In this case, the device is being used as a follower, so I believe a better model would only change the gate voltage a small amount. The low impedance of the complimentary driver seems to eliminate the problems with high input capacity. Is this a reasonable assumption to go on?

The sine and pulse signals are of course generated in SPICE. In the target application, it would be desirable to minimize the transient loading when a probe is touched to a circuit. SPICE makes it easy to evaluate different methods, and a simple rc filter with 1 meg with 5 pf to ground at the input to the op amp looks like it might work. Of course the resistor has to be able to handle the voltage, so five 200V resistors in series might work.

I am looking for very low leakage diodes to protect the input of the op amp. There are some posts in the archives on this topic, and I believe some mention different LEDs may be suitable. Fortunately the voltage across the diodes should be close to zero.

The overall bandwidth is limited by the op amp. Since I am interested in low offset and very low input bias current, I expect the bandwidth to be less than 10 KHz.

I don't expect to be probing 2KV p-p signals at 10KHz anytime, but it would be nice to be able to measure 60Hz without having to change probes. So there is little need to try push the circuit to extreme bandwidths, and the input filter will probably be a convenient place to limit the bandwidth to something reasonable.

The problem of oscillation with high voltage mosfets in the linear region remains. There were a few suggestions in the archives on adding resistors in series with the gate to kill the oscillation, which is pretty much a standard technique.

I did find some references to high voltage amplifiers in AOE, so I am in the process of trying to locate a copy.

Mike Monett

No, because the transconductance of the FET is still very important to the performance, and the bad model is using a value that could be 20 to 100x too high. That's got to have a very serious effect.

I described how you can fix your models. What parts are you using?

That's pretty good. My amplifier is a low-power design, taking only 800mW total from the +1250V and -1200V power rails (so we can power 100 of them with 80W heating). It's not meant for speed, but rather for low noise (0.1ppm) and low Zout. In use it'll drive 60 feet of coax, and I test it with a 3000pF load. With this load it does fine delivering 2200 volts p-p at 150Hz, but it shows slew-rate distortion at 200Hz. At 150Hz 2.2kVpp it's delivering +/-3mA to the 3000pF load. The amplifier is current limited at +/-4mA. -3dB is about 3kHz.