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1Mhz -> 1hz

But 22 flip-flops isn't quite enough, even if two of them aren't in divide by 12 packages

I don't think you mathematical exercise took you anywhere useful

Hmm - ternary logic? I suspose there might be a way of exploiting the fact that a tri-state output can be in three states ...

I'd love to know what you've got in mind.

Nothing complicated about where it was pointing - the puzzling aspect was why one would want to point the OP that way.

A pretty good rule of thumb is to assume the minimum propagation delays to be one third of the maximum delays, but if the manufacturers don't guarantee it, it is risky to rely on it.

Measuring propagation delays before you build the circuit is sort of okay, for a one-off. One very fast TTL system I ws involved with at Nijmegen University relied on exactly that, and the engineer go the system back about once a year as one of other of the ICs had aged enough to take its propagation delay outside the acceptable envelope.

So the researchers didn't have an ESR machine for a couple of days while he shuffled ICs until he'd got it working again. I replaced a couple of critical components with ECLinPS and we got rid of almost a nanosecond of pattern-related jitter, as well as the really tricky race condition.

I essentially completed the design of a properly toleranced system, using a lot more ECLinPS to deliver much better performance, but the grant that ran the ESR machine dried up, so it was never built.

------------------ Bill Sloman, Nijmegen

Reply to
bill.sloman
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We still would be grateful if you showed us the hat out of which you pulled the 12.

But here you go:

Which indeed would be helpful if the OP had asked for the number of divide-by-12 counters he needed to count to a million. But alas, he hasn't.

robert

Reply to
Robert Latest

To go from 1mHz to 1Hz, you need to multiply by 1000.

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 Thanks,
    - Win
Reply to
Winfield Hill 

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Reply to
John Fields

can get to

so what .

You didn't. If you restrict yourself to mod-12 counters, you need six of them, which is 24 bistables.

If you loosen up and use five mod-12 counters and a dual D-type, you still don't get 1MHz down to to 1Hz, though you do get pretty close, without any preloading or decoding.

Quite why anyone would bother to do it that way escapes me.

flip

get you

Don't be silly. I'm so old that I've made bistables with discrete transistors. All the computation I did during my Ph.D. project was done on computers that were built entirely with discrete transistors, and the guy that taught how to program the PDP-8 though we needed to know how to build our own bistables, not that I used his notes when I did need to roll my own.

2,09715200E+006Hz.

Nothing. I do happen to know about decoding the outputs of counters so that they reset before they reach their maximum count. I had thought that everybody who posted here knew that sort of stuff.

If you don't understand decoding, you might be able to undertand how to preset a counter. If you plow through enough of this thread, you will find my suggestion that the OP might use 74HCT40103 8-bit counters which are intended to be used in exactly this way -

formatting link

Have a look and learn something.

Your confidence is amusing.

--
Bill Sloman, Nijmegen
Reply to
bill.sloman

A period of sleep would certainly appear to be involved.

--
 Thanks,
    - Win
Reply to
Winfield Hill

PLL and divide by 1000. Go have a good night's sleep while it locks in.

Best regards, Spehro Pefhany

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Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

Start learning what counters are made of ... then maybe I will answer you

" Go easy on the whisky"

theJackal

Reply to
theJackal

You could use a cheap micro.

It's a single chip solution. Less that a buck. Smaller than a 8SOIC. You choose your own duty cycle. It will still have functionality to spare. Low current consumption.

Thomas

Reply to
Thomas Magma

LOL ... Oh gosh Bill there you go again with your desperado tactics. First you say the best I can get to is 24ffs with mod12 counters. I show you that you are wrong and you say ... so what .

Then you say why point the OP that way. Did you understand his question with flip flops?... He wants a 1 Hz signal ... and do you understand that counters will get you there? Do you know what counters are made of?

You claim that 21 flip flops will get you to 1MHz ... and 2^21 is

2,09715200E+006Hz. Hell whats wrong with you?

Can you tell a desperate man by looking at his face ? I'm sure you can .

"Go easy with the whisky"

theJackal

Reply to
theJackal

How would you multiply 1mHz by 1000?

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Reply to
Frank Bemelman

"Spehro Pefhany" schreef in bericht news: snipped-for-privacy@4ax.com...

flops

I wanted Win to say that ;) I'd think I'd rectify the 1mHz, loooooow pass filter, rectify again, another loooooow pass, and again, until you get a whopping 8mHz and then do the 125 divide + PLL.

I'll think I'm going to have that good night's sleep now ;)

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Reply to
Frank Bemelman

On 22 Dec 2005 15:53:08 -0800, snipped-for-privacy@ieee.org wrote: sniped

OK then it makes more sense to use 21 flip flops to get to over 2hz then add all the hardware to decode that and then bring it down to 1hz .

I think its rather obvious that the easier solution is just use a 6 counters (22 ffs) to get to 1.00hz

Aren't newsgroups for mutual amusement?

"Go easy on the whisky"

theJackal

Reply to
theJackal

In article , Spehro Pefhany wrote: [...]

If you use a tri-state type of phase detector, the lock in time can be only a few hours. If you run the VCO at lets say 1KHz, you can use a bit of trickery to snap the the 1Hz nearly into phase at start-up.

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Reply to
Ken Smith

In article , theJackal wrote: [...]

Bin-there-dun-that:

With easy to get parts, you are limited to a factor of about 5 per stage. Since they aren't flip-flops any more it doesn't change the lower limit on the number of flip-flops, if we assume that all frequency divides are done by the flip-flops.

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kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

Maybe I'm missing something, but the most obvious way to me is 6 stages to divide by 64, then 14 more to divide by 15625 (binary

11110100001001) via a 6 >>sniped

all the

Reply to
tony

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