How to drive 4 output ports with one combinational signal

Hello,

try to use the "KEEP" attribute for each signal.

Regards,

Ivan

snipped-for-privacy@gmail.com wrote:

attribute MAX_FANOUT: string; attribute MAX_FANOUT of A0_O: net is "1";

Hi Ivan and Sylvain, Both of you should get a reward from Xilinx: I get the help within 10 minutes!!!

Thank you.

Weng

Hi Sylvain, signal A0_O : std_logic_vector(12 downto 0); signal A1_O : std_logic_vector(12 downto 0); signal A2_O : std_logic_vector(12 downto 0); signal A3_O : std_logic_vector(12 downto 0); attribute MAX_FANOUT: string; attribute MAX_FANOUT of A0_O: net is "1"; attribute MAX_FANOUT of A1_O: net is "1"; attribute MAX_FANOUT of A2_O: net is "1"; attribute MAX_FANOUT of A3_O: net is "1";

Still error: parse error, unexpected OPENPAR, expecting COLON

signal A0_O: std_logic_vector(12 downto 0); signal A1_O: std_logic_vector(12 downto 0); signal A2_O: std_logic_vector(12 downto 0); signal A3_O: std_logic_vector(12 downto 0); attribute KEEP: string; attribute KEEP of A0_O: signal is "true"; attribute KEEP of A1_O: signal is "true"; attribute KEEP of A2_O: signal is "true"; attribute KEEP of A3_O: signal is "true";

Still error: parse error, unexpected OPENPAR, expecting COLON

All attribute statements are below the definitions of those signals.

Thank you for further help.

Weng

wrote

If you are using XST, disable "Equivalent Register Removal" in the Xilinx Specific Synthesis Options.

Michael

cut & paste from some of my code that works :

--- cut --- signal rnd_ctrl : std_logic;

attribute keep : string; attribute keep of rnd_ctrl : signal is "true";

--- /cut ---

so it's signal instead of net your right but it should work ...

note that I'm not sure if the "keep" will be useful for you ... the max_fanout looks a better option.

Sylvain

Hi Sylvain, Thank you for your help. The grammar now is working.

signal A0_O : std_logic_vector(12 downto 0); signal A1_O : std_logic_vector(12 downto 0); signal A2_O : std_logic_vector(12 downto 0); signal A3_O : std_logic_vector(12 downto 0); attribute MAX_FANOUT: string; attribute MAX_FANOUT of A0_O: signal is "1"; attribute MAX_FANOUT of A1_O: signal is "1"; attribute MAX_FANOUT of A2_O: signal is "1"; attribute MAX_FANOUT of A3_O: signal is "1";

Now the second problem seems to be more serious than the first compilation. When I don't use MAX_FANOUT, the combinational goes to a register that is allocated in the geometric center of 4 output ports. TS_clk66m = PERIOD TIMEGRP "clk66m" 15 ns | 15.000ns | 14.886ns | 8

*TIMEGRP "SDRAM" OFFSET = OUT 8.1 ns AFTER | 8.100ns | 9.184ns | 1

Now with introduction of MAX_FANOUT

• TS_clk66m = PERIOD TIMEGRP "clk66m" 15 ns | 15.000ns | 15.468ns |

9

• TIMEGRP "PCI" OFFSET = IN 3 ns BEFORE COM | 3.000ns | 3.791ns |

1

• TIMEGRP "SDRAM" OFFSET = OUT 8.1 ns AFTER | 8.100ns | 9.042ns |

1

That is what I was expecting when I was writing the first post: For example, in my case, My running timing requirement is met, but clock-to-output timing is violated. If all registers are located in I/O blocks, clock-to-output timing may be met, but the running frequency may be violated. In that situation, all 4 registers should be located near I/O blocks to meet both timing requiments. Not like current case that either one register is located in the geometri center or in I/O blocks.

It seems now I need a Xilinx Field Engieer to help for the new attribute.

Weng

Michael Rhotert wrote:

Hi Weng, In the XST Properties under the Xilinx Specific Options you find "Pack I/O Registers into IOBs". The default value is Auto. Maybe setting it to Yes improves the synthesis result. Also, as mentioned before by Michael Rhotert, you may disable the "Equivalent Register Removal" option.

Also you should check if your CLK66M can be routed to the IOBs. Is it on a global clock net?

Have a nice synthesis Eilert