hi is it a good practice to generate a pulse strobe in Verilog with this code? or do i need to write a fsm for such applications?
BoardConfigReceivedStrobe is set elsewhere in the process. for resetting this signal after some delay, I used this code,I 'm skeptical that this code is not efficient
if(BoardConfigReceivedStrobe) begin DelayCounterBoardConfig100) begin DelayCounterBoardConfig
For a fixed count value like you have a more efficient way of counting is usually an LFSR. Since a binary counter to 100 as you have now is not really that large to begin with it may not save you all that much.
Kevin Jennings
usually an LFSR. Since a binary counter to 100 as you have now is not really that large to begin with it may not save you all that much.
The only thing that looks unnecessarily complex is the magnitude comparison "> 100" instead of an equallity comparison like "== 101" which should give the same results unless your counter increments outside of the posted part of the logic.
-- Gabor
usually an LFSR. Since a binary counter to 100 as you have now is not really that large to begin with it may not save you all that much.
Actually using > can result in less logic than =. Take for example >96. You would only need to compare to "11-----" (two bits) rather than the full seven bits. Not always less, but sometimes.
Kevin Jennings
You mean >=96, of course.
I'm wondering if it wouldn't be faster to compare on zero, load with 100, and count down.
-- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
Loading with a value and using the carry chain for compare (up or down) often works faster, but this is quite dependent on the architecture. In a Xilinx FPGA, the carry chain logic is quite fast compared to LUT's, but most CPLD's only care about how many product terms the equation needs - equality comparison generally only needs one - and that affects the size of the logic more than speed (you hit a speed bump if you exceed the product terms you can have locally for a single macrocell).
-- Gabor
Don't compare at all. Use a signed count value with one extra bit, start at N-2, count down, and stop if highest bit is set (or reload in your case).
Of course you do (and you did). Anything involving a delay must have state (continous or discrete) and if you can build it, it also is finite.
Kolja Sulimma
Am 05.07.2012 17:37, schrieb Kolja Sulimma:
In principle, this should not make a difference. The counter must compare the lower bits anyway to decide whether to toggle the higher bits.
Thomas
00,
Exactly. And if you are smart you define the counter in a way that the same adder can be used for both instead of using two adders. (The solution described by my parent poster compares =3D=3D0 and
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