Hello all, i am using the Spartan 3 (XC3s200). I have a clock signal coming into my FPGA expansion port and all i want to do is have the exact same clock signal going out of my FPGA, just delayed by about 3 micro seconds.I am using verilog and ISE 6.3. What is the best way to do this ???????. Thanks !!!!!!!!!!!
Do you really mean 3 microseconds? That's a *LONG* time in a Spartan3. What is your input clock frequency? Do you have another clock running at a much higher frequency?
If you really mean 3 microseconds, and you have a higher frequency clock I would suggest using a shift register. If you meant 3 nanoseconds, you need to use a DCM, preferably with external feedback, and use the phase shift of the DCM to get your delay.
The best way to do this depends a lot on the nature and frequency of the incoming clock, the aboutness of the 3 microseconds, and the degree of sameness required on the output (once we agree that the word exact in this context can never be achieved).
One example might be a clock of > 10us with somewhere high and low times of
example a 30 stage shift register running off another 10MHz clock might be the best solution.
For another example, requiring 10ns accuracy, triggering alternate 3us counters clocked at 100MHz on rising and falling edges might be a better solution.
Cheers, Alf
-- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324
Make the clock frequency 1MHz (say). Then just connect the clock straight through. It'll look just like it's been delayed by 3us. HTH, Syms.
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hi, sorry, i should have mentioned the clock frequencies. Basically, the signal coming in is an "adcbusy" signal from an ADC converter. 1 - Busy
0 - not busy (take data). This positive cycle on the adcbusy signal lasts for about 1 micro second, followed by an 8 micro second negative cycle and so on.. This is the signal i want to reproduce on the output but with a slight delay. My Spartan3 is working at a woping 50 Mhz (20ns) however.I need to transmit the data to the PC in 1 micro second bursts, the same time as the adcbusy poitive cycle. Thats why i am trying to reproduce it at the output, but a delayed version.
....Cheers!!!!!
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