why is freq Internally divided in uPs?

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Ive studied the Intel 8085 and the 8051 as part of my curriculum. Im
curious to know why in both of these devices, the clock that is applied
to the device is internally divided by 2? why is half to clock value
not given instead?

Thanx in anticipation


Re: why is freq Internally divided in uPs?
I guess that they don't teach much about architectures these days. Did
you mean that the instruction rate is half the clock rate? I don't know
about those particular processors but for instance you might need one
clock cycle to fetch an instruction and at least one to execute it.
Older cores needed lots more clock cycles, maybe 12 and newer ones
might use 4 or even 1 by using techniques like multiple fetch,
pipelining and different architectures.

Re: why is freq Internally divided in uPs?
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That is probably because the internal circuit requires a symmetrical
clock, i.e. duty cycle 50:50, which is most easily achieved by dividing
the external clock by 2. Crystal oscillators are often not symmetrical
enough. 70:30 is rather common and even 90:10 is not too unusual for a
duty cycle. The underlying reason for the requirement of symmetry is
that often both clock edges, i.e. rising and falling edge are used.

Re: why is freq Internally divided in uPs?
hmmmmm......makes sense...:

"There are no requirements on the duty cycle of the
external clock signal, since the input to the internal
cheking circuitry is through a divide-by-two fiipflop."

thanx guys!

Re: why is freq Internally divided in uPs?
Hi Mayank,

This isn't the case for all processors. The MSP430 allows to drive
things like the timer divider chain at full clock speed. It is not a
huge problem to devise a circuit that provide a duty cycle that is very
close to 50%.

Regards, Joerg


Re: why is freq Internally divided in uPs?
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I think they were originally designed using a two phase non overlapping
Every odd cycle would enable PHI1
and every even cycle woudl enable PHI2.

A D Flip Flop would be implemented uisng two latches.
Latch 1 would open on PHI1 and Latch 2 would open on PHI2.

Best Regards,
Ulf Samuelsson   ulf@a-t-m-e-l.com
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Re: why is freq Internally divided in uPs?

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Don't assume that all devices act like the ones you have studied.
For example. the Analog Devices ADuC832 is an 8051 that uses a
32.768 kHz crystal to generate a 16.777216 MHz clock (yes, I did
mean kHz and MHz - no typo), or it runs at 16.7 MHz +/- 20% with no
crystal at all.

Guy Macon <http://www.guymacon.com/

Re: why is freq Internally divided in uPs?

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The reason many processors have higher frequencies (usually 2, 4 or 8) than
the instruction clock has to do with the implementation of the circuitry in
the processor itself.

One of the reason is that different internal operations are performed on
different clock edges. Adding 1 to a register might entail reading the
register into the ALU, incrementing the ALU and writing the ALU back to the

Another reason involves accessing external memory and/or peripherals. It is
much easier to generate access sequences. For example: select the proper
direction of the data buffers on the first clock; assert the external
address and R/w* on the next; assert an address-valid signal (for
generating chip selects) on the one after that; then finally clock the data
from the external device into the processor.

Another still has to do with managing variations in the manufacturing
process used to produce a particular processor. Clocks are convenient ways
to resynchronize signals with varying propagation delays. The also make for
a more consistent interface to the real world. For example, different
address signals routed around the process might actually have quite
different propagation delays to the IO buffers that drive the processor's
physical pins. But, throw in a clocked register at or in the IO buffer and
now all the address signals have nearly identical timing (at the interface
to the real world).



Re: why is freq Internally divided in uPs?
On 27 Dec 2004 23:04:20 -0800, "funkymunky"

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   Having learned on a 6502, I often wondered that myself about other
microprocessors. In the 6502, the oscillator frequency IS the internal
clock (and it has the on-chip crystal oscillator circuit, just like
most other such chips). It usually does a memory fetch or write on
every clock cycle, so many instructions took only as many clock cycles
as they needed memory accesses. The minimum was two, so one-byte
instructions such as register-to-register transfers and no-op take two

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Re: why is freq Internally divided in uPs?
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That corresponds to a classical processor design: read the
instruction, memory access for one operand if necessary,
perform the operation, write the result to memory if
necessary.  This gives from two to four "main" cycles to
execute an instruction.  These "main" cycles don't
necessarily correspond to an oscillator frequency and
usually don't.

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