efficiency

Simon schrieb:

Hi,

you should look up the various addressing modes for both processors and compare the instruction length, the execution time and the maximum addressing distance.

Bye

One thing to look at with interrupts is how the architecture affects the saving/restoring of critical CPU registers. There are essentially 3 classes of interrupt routines:

1. Simple return from interrupt (Ignore interrupt #1)
2. Needing to set/clear a bit in a register to acknowledge the interrupt, then a return (Ignore interrupt #2)
3. Having to do something like transfer some data to a buffer, then ackowledge the interrupt and return.

Depending on the architecture (typical instructions), what registers need to be saved/restored for each type?

I suppose you can determine this from the datasheets once you define efficiency. How do you define the efficiency of an address mode? Number of CPU cycles per access? Number of addressable bytes? Cost of loading an arbitrary byte address? Cost of loading at pointer+offset location? Cost of an indirect load plus incrementing the pointer? Number of cycles per byte to do a block move?

Thad

I don't want to mislead you, but this is the way I see it...

When a PIC interrupts, then the very next clock cycle (or is it the

2nd next?) will go to the interrupt vector. There are around 6 or so housekeeping instructions you must issue before you can actually get to the meat of the ISR. But as far as interrupt latency, I believe it is the very next instruction clock once the interrupt hits.