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For David Eather et al: some "Simple Headphone Amp" ideas

Here are a couple of ideas for parts-count-limited headphone amps that I came up with.

#1, using 5 active devices:

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I liked the idea of an inductive loaded output, as John Larkin's amp had. But I don't want to pay for an audio frequency inductor! This one uses a bootstrapped N-channel MOSFET as a constant current source to simulate one. The same bootstrap is used to provide gain to the previous stage. It's class A single ended but also incorporates negative AC feedback and DC stabilization into the same loop.

Unfortunately, this circuit's output swing is limited because the vertical MOSFET models provided by LTSPice all have a pretty high threshold voltage. In a real application it would probably have much better output swing with audio lateral MOSFETS with lower threshold voltages, but the parts values would have to be adjusted.

#2, using 4 active devices:

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Class A push-pull. Same thing about MOSFETS with high threshold voltages goes for this circuit. Tweak the R12 and R14 pots until the output is centered and the quiescent current is approximately half of the peak output current. I'm less confident about how well this one would perform; R2 and R3 and R1 and R4 would have to be matched.

Reply to
Bitrex
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Private email me. I have no interest in discussing any of this on usenet.

Reply to
David Eather

How about a small step-up transformer and a single mosfet follower?

John

Reply to
John Larkin

one

An opamp and two resistors would be cheating?

-Lasse

Reply to
langwadt

Well, that _is_ really simple...but I wonder what the frequency response would be like. The above designs have enough negative feedback so that the frequency response looks pretty much flat over the audio range.

Here's a relatively inexpensive audio step-up transformer that could be used in such a design:

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Reply to
Bitrex

What is "virgin" copper?! Marketing bumf?

Reply to
Wond

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made from ore, not recycled metal does it matter? don't know

-Lasse

Reply to
langwadt

one

Off the top of my head, I see no reason for a lateral mosfet to have a smaller threshold than a vertical fet. I'm pretty sure nobody sells a native threshold mosfet these days. Probably the vertical flow mosfet manufacturer is more concerned about leakage, so they tweak the threshold on the high side. The manufacturer of the audio lateral mosfet knows the device will never be used in the off state, so a lower threshold is fine.

I suspect the lateral fets are more rugged. Generally vertical devices are more sensitive to crystal defects. That is one of the reasons you don't see wafer scale bipolar circuits. Even if you could handle the heat, the yield of wafer scale bipolar would be low.

Reply to
miso

Interesting insight about the threshold voltages. I just knew from perusing the datasheets that the vertical devices always seemed to have a higher Vt than the lateral devices. I'd really like to have the time to study a course in semiconductor physics; there's one available here:

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The problem with prototyping these circuits now seems to be actually finding lateral MOSFETS for a reasonable price, Toshiba still seems to have audio MOSFETS listed on their site but I can't find them at any distributors. I liked the specifications on the 2Sk2013 but can't find them anywhere but eBay, I found some 2sk1058s and their P channel counterpart on sale here:

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But the prices...:( I guess there just isn't a large enough market for them.

Reply to
Bitrex

On Mon, 7 Mar 2011 12:00:59 -0800 (PST), " snipped-for-privacy@sushi.com" wrote: [snip]

You must be awfully young, or live under a rock. What makes you think wafer scale bipolar would be low yield? ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

      Remember: Once you go over the hill, you pick up speed
Reply to
Jim Thompson

Probably some lame assed term a company like "Monster" came up with.

It is as retarded as anyone that buys ANY of their CRAP is.

That goes for any company (or buyer) that followed along with the dumb shit too.

Reply to
SoothSayer

=A0 =A0 ...Jim Thompson

=A0 =A0| =A0 =A0mens =A0 =A0 |

=A0 | =A0 =A0 et =A0 =A0 =A0|

=A0|

=A0 =A0 =A0 |

You don't know what I know. Even if you didn't know about vertical versus lateral current flow and related defect density, how could anyone forget Trinity? The venture money couldn't flow fast enough, but those clowns didn't know semiconductor physics. Even if you could cool the product, it would never yield.

Reply to
miso

[snip]

Back when epi was 30u thick and emitter sizes were 25u x37.5u ?:-) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

      Remember: Once you go over the hill, you pick up speed
Reply to
Jim Thompson

I

is one

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e

If you look at the construction of lateral versus vertical fets, the vertical is twice as dense since the drain is all on the bottom. If you are selling a power switch, vertical is the way to go.

Most of the time when you lay out a power fet on a chip, it is a waffle pattern. The current flow is still lateral, but it doesn't exactly resemble the diagrams you see in text books. Unless you are going to design analog chips, I'm not sure a course in semiconductor physics is all that useful for a circuit designer. It is way worse than watching sausage being made. I'm not sure how well someone could learn semiconductor physics on their own. Nothing in semiconductor physics is very intuitive.

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1_PhD_thesis.pdf This is a shockingly practical PhD thesis. The guy has some variation on the waffle that looks like it has merit. Anyway, it is a nice history of power devices.
Reply to
miso

Trilogy, wasn't it? (Trinity was the other big explosion.) ;)

Wafer scale anything is a crock--there's no way to get enough leads on it, for one thing--your board would wind up being a foot thick just to escape all those traces.

Anything bigger than 20 mm square is a packaging nightmare for that and many other reasons--and it's even worse now that we have to use higher temperature solder. Keeping the corner pads from breaking loose is hard enough already. Not to mention all those decaps.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net
Reply to
Phil Hobbs

s

nk

=A0 =A0 =A0 =A0...Jim Thompson

=A0 =A0 =A0| =A0 =A0mens =A0 =A0 |

=A0 | =A0 =A0 et =A0 =A0 =A0|

=A0 =A0|

=A0 =A0 =A0 =A0 |

=A0|

|
d
t

That's what I get for not googling! You are correct.

Even in MOS, the trend is to go for finer geometry rather than bigger chips. If you think about it, if yield wasn't an issue, a bigger chip would be the obvious choice. You get to use the old process, which obviously is cheaper than building the next generation fab. But yield falls off dramatically with die size.

Now photosensor arrays is a technology where you really can't scale. Bigger is better.

Regarding leads on wafer scale, there is a great incentive to put as much circuitry on the chip as you can since the pin drivers require beefier fets. Everything on the chip is faster and lower power. Talking to the outside world take power.

Reply to
miso

I agree with you about yield--the sweet spot always seems to be about 20 mm square. (Even for imagers, you can get enough Marketing Megapixels in there for almost anything.)

You chip guys never take packaging seriously. The thermal expansion mismatch, board flex, wafer flatness, and so on are huge problems. Not to mention the power density.

Rent's Rule says that you need more bandwidth as you have more gates (albeit the BW grows slower than the gate count), so getting all those traces off bigger chips is harder and harder.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net
Reply to
Phil Hobbs

Except that now they are (Cymer) using UV liquid photo-lithography. The switch to liquid gave them a whole new window bottom.

Reply to
SoothSayer

Litho has been the main driver of circuit density increases since forever. It's one of the causes of the difficulty we're discussing, not a solution to it. (Due to the failure of scaling, there's been a lot of trouble keeping the devices working as their dimensions shrink, so the device folks are getting a bit more respect these days.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net
Reply to
Phil Hobbs

20

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When they talk about X-ray lithography, my first thought is how exactly do you block an x-ray. OK,. lead apron, but at silicon dimensions?

KLA supposedly has a rapid e-beam litho scheme. No masks required. Reality? Who knows.

Reply to
miso

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