Accuracy of resolver required for PMAC motor computation

Most of the motors we deal with have motor full blown resolvers for motor commutation. The design engineers are wringing their hands about the required resolution for the R2D conversion. I know it doesn't require 16 bit resolution but how low can you go.

Assume 10,000 RPM with a 10KHz PWM and sample rate. This will be FOC controlled with a inner PID phase current loop and external PID speed loop.

How much quantization error can I tolerate in the resolver before it shows up as inefficiency > ~5% or excessive torque ripple?

Reply to
mook johnson
Loading thread data ...

Well, I'd guess 1 _electrical_ degree would be more than sufficient, so 7 bits + log2(pole count) but it may be possible to use algorithms to deal with lower resolution. There are a bunch of papers on dealing with misaligned Hall sensors and you could also look at the claimed sensor alignment of high quality motors (eg. Portescap).

Best regards, Spehro Pefhany

--
"it's the network..."                          "The Journey is the reward" 
speff@interlog.com             Info for manufacturers: http://www.trexon.com 
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

My intuition tells me that's way more precision than you need -- I suspect that the efficiency of that part of the thing is going to go with the cosine of the angular error, which means that at 95% efficiency you're at a bit over 18 electrical degrees. So more like 5 bits + log_2 (poles).

I'd have to sit down and do some real live math to figure it out for sure.

--
Tim Wescott 
Control system and signal processing consulting 
www.wescottdesign.com
Reply to
Tim Wescott

You may be right. ISTR seeing an accuracy spec of 5 degrees for the Hall sensors on some high end Swiss motors (which would be right in the middle of our guesstimates), but I could be remembering wrong. The quantization might be more (or maybe less) objectionable than the type of errors you get with Hall sensor misalignment.

So, assuming a 2-pole motor, 6 to 8 bits?

Best regards, Spehro Pefhany

--
"it's the network..."                          "The Journey is the reward" 
speff@interlog.com             Info for manufacturers: http://www.trexon.com 
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

Y'know, thinking about it, 5 bits for a two-pole motor. At absolute minimum -- mo is better, of course.

Given that 12-bit ADCs are practically free on microcontrollers these days, and that even when you figure that's 10 bits of accuracy and two "marketing bits", I think Mr. Mook is home free on this one.

But -- I'd have to run them numbers.

Mook -- please tell me they're not messing around with hardware R to D converters.

--
Tim Wescott 
Control system and signal processing consulting 
www.wescottdesign.com
Reply to
Tim Wescott

You got it. Firmware guy wants a 16 bit RDC that ADI sold him on. :)

You are also correct the internal ADC is good for ~ 9 bits with a few marketing bits....I like that. :) I gotta remember that one.

From foggy memories I suspected there was a cosine theta in there based on the magnetic field vector angle to the stator field vector being 90 degrees for max torque (makes since). Either side of that was flux weakening or something else but you got less torque per amp in either case.

Answers my questions and suspicions to a T. Thanks guys!!!!!!

Reply to
mook johnson

If you're going to get into any scraps with this, point out that in addition to being expensive, those RDC's need quite a bit of care from the circuit designer to achieve an honest 16 bits, particularly if the motor is going to be subject to a great deal of acceleration. The RDC process that they do (at least if it's the AD2S80 or some derivative) is "phase-lock-ish" in that the chip continually generates a sine and cosine wave from the reference, based on the estimated phase, then increments or decrements the phase counter based on the value of a derived error signal. This means that to lock onto a continually rotating shaft you need to have an integrating loop filter, and when you do that you slow down the response to acceleration.

Just throwing the chip down with a few parts may very well end up with several degrees of error just from the RDC estimate lagging the actual shaft angle. Getting better performance requires at least as much care and understanding of the issues as does sampling the two coils of the resolver with ADCs and doing the sine-cosine to resolver conversion in software.

Also, if they want to use one of those parts, be sure to double-check on how easy it is to synchronize the RDC to your loop: my recollection is that you need to feed the thing a clock, which you would want to be synchronized, and there's all sorts of clock rate vs. performance trades.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com
Reply to
Tim Wescott

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.