Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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How to simulate baud rate generator?
I've gotten the following code for the baudrate generator from opencores I've created a Test Bench Waveform for it from my ISE. Using single clock, Rising edge, Clock High/Low time as 3, Input setup/...
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15 years ago
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ps2 mouse initialization fails
Hi, I tried out 2 mouse modules. Both get stuck in the mouse initialization process. The mouse does not respond. The modules i tried out are : 1. (gets stuck in state "send") 2. from the book "FPGA...
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15 years ago
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VHDL code for DDFS
hello, i want a simple VHDL code for DDFS. its really very urgent. anyon who is having that VHDL code plz plz send me as soon as possible. thank you! my email address is
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15 years ago
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multicyle and false path in FPGA Design
Hi All, How to identify the Multi cycle path and the False path in the design. do we need to identify after the Synthesis stage xilinx fpga tool it self will recognize and through as warning or error....
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15 years ago
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Help with Microblaze timer peripheral
Hi everyone, I am a begginer with microblaze, and I am trying to do some practice code in a Spartan3 Development Boards. I want to program a counter with the opb_timer and print the counter every 0.5...
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15 years ago
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Chipscope data port limitation to 256 bits
Hi I have a bit a problem, I would like to capture the status of 16 registers in my architecture each of them 32 bits long. However, if I try to integrate an Logic Analyzer the maximum datapath that I...
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15 years ago
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Low cost solution to program Spartan 3AN DSP development board AES-SPEEDWAY-S3ADSP-SK
Yes, how many times I don't write here, maybe about 6 years, from my thesis on a qpsk modulator on a Virtex 1000, I don't know if they still write here but in the case my greetings to Ray Andraka and...
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15 years ago
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Dynamic partial reconfiguration on virtex devices
Hi all, I'm working on dynamic partial reconfiguration on a virtex 4 (sx35) fpga. I would to use hwicap to make internal reconfiguration. Do you know if a bus macro with enable signal is necessary?...
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15 years ago
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Call for participation in VLSI 2009 in New Delhi.
Friends, As you all know, the 22nd conference on VLSI Design would be held in New Delhi from January 5 to 9th 2009 at The Hotel Taj Palace. The theme for the conference is "Improving Productivity...
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15 years ago
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oversampling serializer?
Hi everyone, I'm supposed to implement a serializer where the parallel data and clock arrive from outside the chip and I have an 8x internal clock which is frequency locked to the incoming clock but...
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15 years ago
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Question: What are the tricks mentioned on Viterbi Decoder Wikipedia page?
On this wiki page on Viterbi Decoder : In the TBU section, it reads "Note that the implementation shown on the image requires double frequency. There are some tricks that eliminate this requirement."...
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15 years ago
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logical net 'NET' has no load
Ive seen posts on this error in VHDL a few times around here, but I am still unsure how to get rid of this error so my nets don't get removed. Here is the code that is causing the error: library ieee;...
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15 years ago
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Xilinx ISE impact outputs bad idcode when in batch mode but works in gui mode
Hi, I am trying to create a batch file to load a bit file into an FPGA (Spartan 3E 500 -5 PQ208). I used the following commands: setMode -bscan setCable -p auto addDevice -p 1 -file...
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15 years ago
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Regarding Xilinx tool
My name is vignesh. I am also new guy to Xilinx .. i want to know the following things... please help me... 1. how can i create the *.ucf file using xilinx Tool ? (if you have provide me ) 2. how can...
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15 years ago
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Configure registers of CMOS Sensor by Spartan3
Hi, I am trying to configure the registers on the MT9T001 Image sensor using a Spartan3 board. I fed a 50MHz to the SCLK, the SDATA is pull-up by 3.3V, and after feeding the start bit and 16bit...
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15 years ago
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