Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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The littlest CPU
I may need to add a CPU to a design I am doing. I had rolled my own core once with a 16 bit data path and it worked out fairly well. But it was 600 LUT/FFs and I would like to use something smaller if...
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15 years ago
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Additional Hardware Module with Xilinx MicroBlaze Processor
Hey all, I have a Xilinx Spartan-3E starter board, and I'm implementing a MicroBlaze processor on the FPGA. I would also like to use the LCD which is on board, and I have already developed a hardware...
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15 years ago
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Virtex-5, DDR2 SRAM, and ISERDES
Is it not recommended to use the ISERDES in the Virtex-5 to perform strobe-based read capture from a DDR2 SRAM (not QDR) part? I'm routing my echo clock (CQ) into the FPGA through an IODELAY...
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15 years ago
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Which FPGA has most ram in a TQFP144 or smaller non-BGA?
Which affordable FPGA has the most dual port block-ram type resources in a TQFP144 or smaller quad flat pack (non-BGA) package, that's actually stocked by distributors? I/O requirements and internal...
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15 years ago
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free video course fpga or asic
Hi every body, I am new to fpga design and I d like to know if there is anyone who knows where I can find free video course on fpga or asic. thanks in advance for your reply, dabaf,
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15 years ago
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ml403_emb_ref_ppc_81.zip problem
My problem is explained here... While creating the new XPS project using Base system Builder: Step 1. New Project->Base System builder Project-> Create a new XPS project using Base system...
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15 years ago
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a question about linker map file
Hi, I'm currently working in a POSIX thread management and synchronization library upon xilkernel + (powerpc/microblaze). This library really provides to user all thread-related xilkernel services...
2
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15 years ago
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Problem creating the ML403 project using Xilinx tool
Hi Guys, I am new to Xilinx tools. I am facing some problem while creating the "Base system Builder project" for ML403 Rev B board. The steps as follows: 1. I have downloaded the...
8
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15 years ago
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8 | |
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verilog code
module chkchk(buff1,len_tcp,src_addr,dest_addr,word,word32,tcplen,prot_tcp,led1,led2,sum); input [159:0] len_tcp; input [31:0] src_addr; input [31:0] dest_addr; input [255:0] buff1; //input [255:0]...
5
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15 years ago
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Free Seminar on Advanced Verification with Aldec’s Riviera-Pro
Free Seminar on Advanced Verification with Aldec=92s Riviera-Pro Given the ever growing complexities of SoC designs, the task of verifying these SoCs is herculean indeed! A series of innovative, path...
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15 years ago
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Need help regarding xupv2p board....
I bought this board so that I can write the whole software using just VHDL. but only info i can find is... to use Power PC or microblaze core using EDK and then have periphirals using VHDL. I tried to...
1
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15 years ago
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USB 1.1 Function IP Core
If any one use USB 1.1 Function IP Core from opencores site please tell me this core has bugs or not.
1
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15 years ago
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1 | |
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example of counter for chipscope pro generator
Hi everey one, i am new to chipscope pro,i worked with verilog example of counter,and instantiated vio,icon and ila works i want to try with vhdl.i have written a counter program in vhdl and when i...
1
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15 years ago
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timing constraint - XPower 9.2 problem
Hello, I implemented a design which uses DCM in Virtex-II Pro XC2VP30-7. I have used ISE 9.2. for design implementation. In the constraint .ucf file, I put the timing constraint for DCM to be 10 ns....
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15 years ago
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UTMI
Please tell me if any one know links or have UTMI interfacing core free of bugs in verilog. Please tell me if any one know functionality or timing diagram of UTMI interfacing in usb core. if any knows...
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15 years ago
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