Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Best syntheses
Hi, I have been using Xilins XST for a while and have come to a performance problem which leads me to think of if there is any better syntheses like Synopsys or other. The device is a Spartan3 4000 an...
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J1 forth processor in FPGA - possibility of interactive work?
Hi, I'm very impressed with a J1 forth processor: 'd like to use it to implement simple non-time critical control and debugging layer in my FPGA based DSP system. However to accomplish it I need to...
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DDR SDRAM Configuration problem on XUPV2P
Hi! So, I'm using XUPV2P board (). And I'm having a problem setting up my DDR SDRAM module to work properly (it never passes Memory Test). Memory module that I'm using is : Hynix HY5DU56822BT-D43(...
 
FPGA cards with memory bus interface
Good day everyone I am fairly new to FPGA based architectures, and I'm interested in applications that are very sensitive to IO bus latency (PCIe or FSB). Can anyone advise of FPGA cards that can plug...
 
fpga
Hello dear all, I have run into a problem regarding the FPGA. The FPGA output signal amplitude is 3.3, and to drive my switches, I need to increase the voltage up to 15 V. I am using TC4427(dual power...
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USB support for XUPV2P
Does any one know an add on card that can be used with XUPV2P?
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Why feedback clock in SDRAM controllers?
I see it in many SDRAM controllers, e.g. ftp:// and nobody explains WHY The extranal feedback trace must equal to CK len. Ok. This means that SDRAM will be clocked in phase with the FPGA system. How...
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Soft Processors and Licensing
Just a bit about the project I'm working on: Have an FPGA gathering and manipulating data, and we need a processor to run the show and to send the data over a network. At the moment we are planning on...
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boldport
In a bit of a self promotional move, though probably pretty relevant to this group, I'd like to mention which I released on Monday, and for easing the migration from GUI to command-line use of FPGA...
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remove Xilinx webtalk
Hi, How do I remove webtalk in Xilinx 13.1, I do run all the tools from a script not from GUI? I did run a trail license at first but now I have a proper flexlm license! /michael
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NULL POINTER DEREFERENCE
Hello all, I am a fresher in this industry..... I am working on systemverilog... I have created a model for analog to digital conversion,I have to make use of an already created model I have made the...
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ise 10.1 (Linux) contraints problem
Hello, all, I'm using Xilinx Ise 10.1 on a Linux system, and ran into a crazy problem. I took a previous design and stripped out a bunch of stuff to make a skeleton of that project to test something,...
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Logic Accessible Clock
The Logic Accessible Clocks are entailed for example in I do not see much explanation of the concept. But, I would expect some when sys_clk_fb is registered by in-sync clk2. Sinse both clocks switch...
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Re: Lattice Breakout Boards
Interesting offering from Lattice again. Too bad the price is quite different from $29 for those of us on the wrong side of the pond...
 
Re: about slices in xilinx
are of order e Wow, I don't know homework can be done easily online today. The question is, does he remember anything afterward ? I think he does
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