Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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verilog task and vhdl
Hi all, I've a functional model of a PHY chip in verilog with a lot of tasks to stimualte change on signals at the interface (and not only)... Unfortunately I'm not experienced with verilog...I would...
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12 years ago
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Connecting of IP core simulated in GHDL to pseudoterminal via UART-like interface
When working with simulated soft CPUs to be implemented in FPGA, I often needed a possibility to connect terminal emulator (e.g. Minicom) or my own program to serial port of the simulated IP core....
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12 years ago
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How could I get LUT-level netlist in Xilinx ISE?
Hi, I need to convert the high level design to LUT level netlist, and then make corrections to it. "The translate step generates a Verilog netlist that can easily be parsed. This netlist consists out...
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12 years ago
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Microblaze and PowerPC
Hi, I would like to perform mathematical operations as Division and Square root. From what i have read, i either need to use Microblaze or PowerPC. can anyone please tell me the difference in...
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12 years ago
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FFT using logic gates only
I intend to implement FFT using Logic gates only , by this i mean i have written verilog code of FFT for xilinx spartran III, I can visualize it in Xilinx ISE 13.1 using technology schematic. But its...
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12 years ago
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Random Reset calls
Hi Folks, Need something interesting in random reset: I am having a testbench in verilog which needs to hit the state machines states with reset. Basic Format of testbench: ##############3 initial...
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12 years ago
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Package constants (VHDL)
Historically I have used a VHDL file to embody the constants in a design where possible using meaningful names which can be easily changed. library IEEE; use package constants is constant rck_freq :...
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12 years ago
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please see me
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12 years ago
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Call for Papers (CFP)
========================================================= ARPN Journal of Systems and Software Call for Research Papers Dear Sir/ Madam, ARPN Journal of Systems and Software is an International...
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12 years ago
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Instantiation of an EDF netlist within a Verilog top RTL
Hello Guys, I am working with Synplify Pro. I have a RTL wrapper in Verilog where a module is instantiated. But this module is available as an EDF netlist. How can I include this EDF netlist in my...
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12 years ago
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Records as ports in Synplify
We are trying to implement a toplevel module which has an IN and an OUT port which are records. The synthesis works fine but we have the problem that synplify converts these record ports in a big port...
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12 years ago
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PCI Express Cable
Hi, Does anybody here have experience designing something to do PCIe over cable? I need to design (ie, draw the schematic of) a target device that will have a Molex cable/connector coming in, some...
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12 years ago
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HEART 2011, June 2-3 2011, Imperial College London, Call for Participation
Dear Colleagues, We cordially invite you to join us at the 2nd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2011, a forum to present and discuss the...
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12 years ago
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Fall Times and Pullup
If on a bidirectional bus, if there is a strong pull up and there is a device which is drives the line low, can we reduce the fall time substantially, if we reduce the pull up on the lines? Or is it...
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12 years ago
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comparator fast implementation
Hi, In my design i have two counters, a write_counter and a read_counter, both are 11 bits wide. I used a simple compare equation like this: assign last_byte = odd_number_bytes ? (read_counter + 2 ==...
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12 years ago
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