Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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How to open the interface GUI of ChipScope Pro Analyzer on linux
Hi, I want to using ChipScope Pro Analyzer to check my design. I have already generated the icon and ila cores and connected them with my design. But I am stumbled with how to open the interface GUI...
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12 years ago
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Verilog Custom Core To Read and Write From RAM
I want to add a custom verilog core to an already established pipeline of microblaze. The core should be able to read data from memory locations from DDR RAM (external) which is already present on...
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12 years ago
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Xilinx ISE ignores Max Fanout
I had been working with Xilinx ISE 12.4 for a while trying to improve the performance of a SPARC based processor. Till now, I was always and stopping at the "Synthesize - XST" step. I found that going...
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12 years ago
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ucf file for 32 bit counter spartan 3e S500E -4
I have designed a 32 bit counter but I am having a difficulty in assigning 32 pins to the 32 bits since I don't know the "LOC" (location) of the pins which is required in the User Constraints file. I...
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12 years ago
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[OT] How to save an artifical life..
Hi everyone, I would like to share a youtube clip...one click costs nothing while can save lives sometimes (expecially mine). Thanks a lot and cheers.
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12 years ago
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Sporadic simulation result with modelsim
Hello all, I struggle with an issue I can't understand the root cause. When simulating my back annoted design with modelsim, I get unexpected behavior when using a simulation step of 1ns, but no...
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12 years ago
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Xilinx or Altera
Hopefully not sparking any religious wars here, but hoping for some advice from those-who-know :) I switched to using Altera's software a couple of years ago, because it felt more intuitive to me -...
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12 years ago
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Choosing a scope
Hello, I am trying to choose a new oscilloscope, but also keeping my eye on logic analyzers. I am mostly working with video stream over FPGA, so I need a scope for this purpose. I've narrowed my...
4
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12 years ago
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Determine latency of GTX links vs Aurora+LVDS
I have a design partitioned over 2 FPGAs. I am trying to determine the bene= fits of selecting GTX links vs. LVDS to transfer the data between FPGAs. =20 Target Device : xc6vlx550t Target Package :...
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12 years ago
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Area optimization (optimizing DSP48E usage)
I am trying to map, place & route a large design on a Xilinx Virtex 6 FPGA Target Device : xc6vlx550t Target Package : ff1759 Target Speed : -2 My mapping process fails with the following errors:...
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12 years ago
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What is the advantage of source-syncronization (in SDRAMs)?
The data arrives with some unknown phase shift relatively to system (synchronized to SDRAM) clock. DQ can be captured more reliably if we route the data clock, DQS, along the data. They suggest that...
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12 years ago
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Area Optimization
Hi all, I have a design (written in VHDL) targetting the Spartan 6 series, and it's oversubscribed for LUTs. Can anyone recommend good resources to read? I've already spent a little time looking...
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12 years ago
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Variable Optimized Away
Hello, I am having a problem where Xilinx ISE is trimming away a variable that I need, tempShifts. I can still implement the module but I am not sure what it is doing with my variable. This says to me...
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12 years ago
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multiplication in indexation
Hello everyone I want to do a for loop in order to repeat the same construction and use the number of the loop to create the index to take the desirated part of the bus , the problem is that i don't...
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12 years ago
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Looking for bitgen Virtex7 and Kintex7 support
Hello, It appears that bitgen in ISE 13.1 supports Virtex7 and Kintex7 implementation up to but not including bitstream generation. Does anybody know when bitgen support may be expected for those...
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12 years ago
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