Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
job offer fpga designer genova
we are looking for an fpga designer in Genova with the following knowledges: Operating systems Windows, Linux Programming Languages VHDL, verilog, System Verilog, C++ Tools FPGA synthesis (Precision...
—
|
12 years ago
|
— | |
|
|
Spartan3DSP TphDCM spec question
1) Why the spec calls out negative number for input holding time ? eg. TphDCM = - 0.26 ns 2) What does that means when they say "When the hold time is negative, it is possible to change the data...
9
|
12 years ago
|
9 | |
|
|
How do they handle shorts during the dynamic reconfiguration?
Normally, the tools check that there are no driver conflicts during synthesis and shut down all drivers when start the configuration. Yet, one and the same line can be driven by different drivers in...
6
|
12 years ago
|
6 | |
|
|
small size SDSL modem
Hi all Can any one kindly tell me from where i can get small size (atleast width < 50mm) SDSL modem with ethernet input? Best Regards --------------------------------------- Posted through
—
|
12 years ago
|
— | |
|
|
Help with bidirectional interface of a FPGA with a uC
Hi need to implement a bidirectional 8 bit interface of a FPGA with a microcontroller. For now i am developing with a Ciclone II but i will have to make it for a Spartan-3A too. Inside the FPGA i have...
4
|
12 years ago
|
4 | |
|
|
Ericsson Eurocom D1
Hi, I know this isn't the right place to ask this question, but since i use this forum frequently, i thought i should start from here. Has anybody here worked on Ericsson's Eurocom D1 protocol ? I...
—
|
12 years ago
|
— | |
|
|
[ANNOUNCE] DSP-FPGA Programming Contest
DPStronics ( is hosting a design contest ( DSPtronics Portable FPGA Modules 💥💥Играйте и выигрывайте с Pin Up Казино в Казахстане! Лучшие...
—
|
12 years ago
|
— | |
|
|
What's the black and while round on FPGA slice?
Hi, I implemented a full combinatinal logic in Xilinx FPGA. A white and black eye appears on each SLICE. What does it means?? Thanks --------------------------------------- Posted through
1
|
12 years ago
|
1 | |
|
|
Virtex 5 Rocket IO design for reading in ADC data.
Hello all, I am presently working with a virtix 5 FPGA and trying to get the rocket IOs to work with reading in the data generated from my ADC. The ADC is clocked at 500MHz and I have 5 LVDS outputs,...
11
|
12 years ago
|
11 | |
|
|
JESD204A and Spartan-6 GTPs
Hi, I read the application note ?Virtex-5 FPGA Interface to JESD204A Compliant ADC?. I?m designing a pcb with a JESD204A NXP DAC linked to Spartan-6 GTP Dual tiles. I try to know If I?m actually going...
—
|
12 years ago
|
— | |
|
|
Delta-Sigma in an FPGA
Hey all -- So I've got yet another project making me say "Gosh it'd be nice to be able to implement a DAC/ADC directly in the FPGA." And so I looked around and found all the same white papers I always...
7
|
12 years ago
|
7 | |
|
|
XST 13.1 explodes with generic of enum type with only one member
It was all going so well until I asked XST to compile a VHDL entity with a generic of this type: type video_modes_e is (vesa_1024x768_65Hz); I guess I'll have more modes later, but just now I need...
13
|
12 years ago
|
13 | |
|
|
digitization of sensor array
Hi all I need to digitize a 32 channel sensor array, hosed in a pipe of 50mm diameter and 6m length. Sensors are hydrophones integrated with preamplifiers. Simultaneous sampling is required with...
3
|
12 years ago
|
3 | |
|
|
Depth of logical Circuit
Hi all, I sythesised (with Xilinx ISE) some complex logic circuit just consisting of AND and XOR gates and I am wondering if there is any way I can identify in the post-sythese report the depth of the...
7
|
12 years ago
|
7 | |
|
|
P&R based on the post-map simulation model?
Hi, I need to modify the netlist generated from "Generate Post-map simulation model"(i.e. netgen). After the netlist modifcation, can I continue the work of place&route based on the modified...
3
|
12 years ago
|
3 |