Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Speed attained by virtex 6
Dear sir, I am working on the virtex 6, XC6VLX550T FF1759 speed grade -1 , using finite state machines with high operands, (113 bits), in Galois field inverse theory. The problem I face is that I got...
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sdxc
Anyone familiar with SDXC host controller? I'm not getting the performance I need because I am getting too much delay between writes using CMD25. I'm trying to stream video, do I have to use CMD20 or...
 
Issues with Soft-Cores
Hello. I'm a little bit tinkering with soft core cpus for fpgas, but I really have serious issues doing so. Thats why I decided to ask some experts and register here. I tried to find a efficient...
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RTL timing issue
Hi, I am using a customized board with 1 spartan 3 xc3s4000 FPGA and 2 Gigabit Phys. My system clock is 125Mhz and i am facing an issue which occurs after a while but since it occurs so it is a...
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Very Slow Circuits (Was: Fast Circuits)
Reading 1uHZ as "full stop",... A few geological ages ago, I was debugging a quite complex system based on a Z80 CPU (Fully static design) Things like an ICE or logic analyzer were luxuries not...
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Modelsim script to print simulation progress and a TCL question
A long time ago there was a thread on regarding how to regularly print out some information about the simulation progress. The thread was fairly short and no real progress was made to a solution which...
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Enterpoint Recruiting
It's been a while since I have said this in public but we are recruiting again for our UK office. Details on This one covers a pile of skill bases and open to anyone with a right to work in the EEC....
 
FPGA not getting programmed
Hi, I am using a custom board design in which i have 2 FPGAs (spartan 3 xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like this: EEPROM -> FPGA1 -> FPGA2 Now the problem is that...
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ASM vs. RAM
Hi! Can anyone prompt me what is potential benefit of using of auto-sequencing memory (ASM) instead of standard static RAM? The final interest is ASIC ? die size and power dissipation. I?m sorry if my...
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FSL Problem:Data Return and Use
Hi! I wrote a custom IP peripheral in verilog and interfaced it to MicroBlaze, using Harware>Co-processor option. I can see the peripheral connected on the System Design compile and build is...
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Looking for a FPGA board
I'm looking for a FPGA OEM module for analog signal processing which contains the following: - medium size spartan 3 or spartan 6 FPGA - 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit...
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FPGA input pin connection to receive MIPI CSI-2
Hi. I'm just beginner in making fpga and i want to make MIPI CSI-2 to parallel converter in fpga. i think there are strange point. in mipi spec, there are two mode, LP and HS mode, and these are very...
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XC6SLX150 Coprocessor Modules
Two new FPGA coprocessor modules released today. The initial availability will be modules based on a Xilinx Spartan-6 XC6SLX150 FPGA although we may offer these products with either a XC6SLX45 or...
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Synthesizable heap-sorter for FPGA - BSD licensed sources
Hi, I have prepared a heap-sorter implementation for FPGA. The sources are licensed under the BSD license and are available at group. Due to the fact, that I'm on my holidays, I was not able to post...
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[ANN] HercuLeS high-level synthesis tool
Hi everyone i'm pleased to announce that after two years (and about 2000 man- hours), the HercuLeS high-level synthesis tool is ready for non- trivial work. HercuLeS allows you to synthesize ANSI C...
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