Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Boundary scan
Hi, i wanted to know whether there exists any software that can be used to know whether all the balls of my bga grid are properly fixed in place or not. Actually i am using spartan 3 xc3s4000 and...
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12 years ago
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Very cheap Spartan3 board that can be configured by simple USB
Hi, I would like to know which is the smallest (read cheapest) board with a Spartan3 that can be programmed directly by a usb cable. I just need a couple to test a design that must be operated...
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12 years ago
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cheating Arria FPGA i/o count
Hi, I'm designing a pretty horrible board (33 page schematic!) that will use an Altera Arria II GX in the 572BGA package. There are 240 pure I/O pins in this package, and 12 dedicated clock pins. I'm...
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12 years ago
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ISE and detecting flowthrus
Hi All, When doing multi-FPGA designs, what are some of the techniques that you use to detect if you have mistakenly pin multiplexed a flowthru net? I am specifically interested in the way which ISE...
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12 years ago
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The smallest EDA tool
Robei is the world smallest EDA tool (less than 5Mbits) for Verilog based EDA software. It integrates modern graphical user interface and a tiny cross platform Verilog simulator. The biggest advantage...
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12 years ago
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meta assembler
Are there any commercially available meta assemblers like metalasm for programmable state machines in FPGAs? Thanks Dave
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12 years ago
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Running Chipscope >=12.x on Linux.
When I tried to use Chipscope on my Linux machine, I got, the following error: COMMAND: open_cable INFO: Started ChipScope host (localhost:50001) ERROR: Failed to open connection to server...
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12 years ago
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Regarding virtex II pro xilinx XC2VP30 FF896
Sir I want to know how much voltage(min and max)to I/O connectors of J5 AND J6 in virtex II pro xilinx XC2VP30 FF896 board , can given. Thanks Varun --------------------------------------- Posted...
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12 years ago
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FPGA based PCIe Gen3 Endpoint question
I need to use the FPGA as PCIe Gen3 endpoint on one side and SPI ROM interface on the other side. Normally in x86 PC architecture, the southbridge SPI rom interface integrated but I need to eliminate...
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12 years ago
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vhdl:passing generic sized arrays to functions?
Im have different sizes of std_logic_vector arrays and want to run functions on different array types where vector sizes are different (array height is unconstrained). Ive looked at subtypes, but cant...
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12 years ago
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[actel] resource usage by entity
Hi , I am currently designing a FPGA Actel Proasci3 and I would like to know the ressource usage (ram/flipflop...) for each of module of the project , in Altera and Xilinx they report this information...
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12 years ago
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MAXDELAY constraint
I have a 200 MHz clock gated by a BUFGMUX. I added some unrelated logic and the routing of the gate control signal got longer and broke the FPGA. The routing delay in earlier versions was ~ 1.8ns...
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12 years ago
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VHDL Basic Question
I am new to VHDL and need some advice on connecting a vector array on an entity using a port map.I have an array of std_logic_vectors(63 downto 0) as a port. There are 3 of these in the array. How do...
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12 years ago
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Testbench in verilog ps and human interactions don't mix
Hi all, I am testing a fairly slow design ( a IAMBIC keyer) and while I am dealing with slow signals (up to 120 WPM, about 10ms minimum resolution) I would like to perform very precise measurements...
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12 years ago
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Spartan6 PCB debugging: how badly do you have to screw up for JTAG to not shift?
I'm troubleshooting the first rev of my first Spartan 6 PCB design; this is sort of a learn-by-making-all-the-mistakes process, but I could sure use a hint or two here from the gurus. Obviously there...
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12 years ago
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