Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Job offer for ALTERA FPGA electronic engineer developper
Interested people contact me. The skill: Electronic engineer, TI engineer, Phisics BS or PhD, expert in FPGA design and digital and analog circuits design. Inmediate incorporation. Work in Spain.
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12 years ago
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Minimalist Spartan6-LX150 Board for $250
This may be of interest to
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12 years ago
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Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
I am designing a Spartan-6 pcb with DDR3 by way of Memory Control Block and with various video interfaces. Before I start with my own design, I thought I would look at other available designs,...
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12 years ago
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Browser-Based Timing Diagram Editor
I used to use a really nice, simple, browser-based timing diagram editor, and now I've forgotten the name and URL of this tool. Does anybody know which one I'm talking about? There was a text window...
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12 years ago
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comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA (EP4CE22F17C6N) apples to apples.
the xilinx says it has 500,000 gates, the altera says it has 22,320 Logic elements (LEs) 594 Embedded memory (Kbits) 66 Embedded 18 x 18 multipliers 4 General-purpose PLLs so are these two fpga's...
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12 years ago
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gigabit ethernet problem
Hi, I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2 national Gigabit PHYs. So i receive a packet from phy A and transmit it to PHY B and vice versa. Now the problem i am...
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12 years ago
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Xilinx Spartan-3 Starter Kit and Webpack 13.2
Hello all, I'm just starting into FPGA's, and have access to a Spartan-3 Starter board. Even though it dates back to 2004 and is no longer supported by Xilinx, I expect I should be able to at least...
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12 years ago
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SIM card 1.8V / 3V sensing
Can anyone steer me in the right direction of an article how one is meant to determine if a SIM card is of the 1.8V, or the 3V variety? Many thanks in advance.
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12 years ago
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How to digitize the VGA output using FPGA?
I would like to know if there is a development kit and documentation available to digitize the VGA siganls to create the a digital video fram using FPGA. I see lot of fpga applications that generate...
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12 years ago
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Registers at I/O
Synthesis optimization people seem to like registers at I/O. Particularly, in Xilinx manual: "The synthesis tools will not optimize across the Partition interface. If an asynchronous timing critical...
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12 years ago
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Virtex 6 dev. board suppliers?
Hi, I'm looking for a Xilinx Virtex 6 based dev. board, (with PCIe and SFP connectors for 10G Ethernet). Other than Hitech Global, what other suppliers are there? You suggestions are much appreciated....
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12 years ago
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LFSR in xilinx 13.2
Hi, I am using xilinx 13.2 for my design synthesis and i want to use xilinx IP for LFSR but i cannot find it in core gen. I am using Spartan3 xc3s4000 FPGA. Does anyone know where i can find it?...
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12 years ago
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clock enable for fixed interval
What would be the proper way to clock a register at a fixed multiple of the system clock? I am trying to create a signal that is active around the rising edge of the system clock as a clock enable. I...
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12 years ago
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CONSTRAINTS
Sir When we run our vhdl programme it sysnthesize and implemented witout any error, In place and route report it gives as: Generating Clock Report **************************...
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12 years ago
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Can't get the Xilinx cable drivers installed on SL6.1 (RHEL 6.1)
Has anyone been able to get Impact or Chipscope working on SL6.1/CentOS6/ RHEL6? It failed with the xsetup GUI but it only gave a useless error message that it failed in the log. When I tried to run...
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12 years ago
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