Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Driving crystal with cheap FPGA ( MAchXO2) directly ?
I tireid using ust a pin pair and inverting function. But with LVCMOS333 on Breakout Board ( 3,3V for I/O), MachXO implements hysteresis on input and this seems to hamper the oscillations. I can't...
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3 years ago
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Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?
I can't do it. Every time I try, LSE reports "combinatorial loop" and optimizes whole thing away. I tried using attributes syn_preserve, syn_keep and syn_noprune, but the result is the same. LSE...
6
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3 years ago
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enum and Vivado
I'm clearly failing to understand how enums are supposed to work in SystemVerilog. I've created a header file with the enum definition. I `include that header file in two files that want to use the...
7
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3 years ago
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Looking for MMI M2018 LCA data sheet
Hello, I'm a collector and tinkerer of old, archaic devices, and I recently came across a MMI M2018-20CP (date code 81xx) in a PGA package. I've found the M2064 data sheet, but I can't seem to track...
15
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3 years ago
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15 | |
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fixed point modeling tools
Hello, For those of you who do DSP modeling in Python, I've recently released a pa ckage that supports fixed point arithmetic. The existing open source tools are lackluster and MATLAB doesn't nicely...
4
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3 years ago
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Passing digitized data to design
Hello, Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification? I'm getting int o FPGA development and have created a...
5
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3 years ago
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5 | |
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CFP IEEE International Conference on Computer Design (ICCD) 2020
------------------------------------------------------------------ Call for Papers ------------------------------------------------------------------ 2020 IEEE International Conference on Computer...
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4 years ago
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Custom CPU Designs
I've spent months working around such problems :( We have an application that pushes gigabytes through JTAG UARTs and have learnt all about it... There's a pile of specific issues: - the USB 1.1 JTAG...
8
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4 years ago
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8 | |
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No more gate-level simulation. for Cyclone V !!!
Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful. Now using a Cyclone V I found that I can't do timing gate-level timing...
8
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4 years ago
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8 | |
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PipelineC - C-like almost hardware description language - AWS F1 Example
Hi folks, Here to talk about PipelineC. What is it?: - C-like almost hardware description language - A compiler that produces VHDL for specific devices/operating frequencies I am looking for: - anyone...
2
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4 years ago
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Using EDA tools at home
Need to use your company EDA tools from home, here are some tips: 1) First of all, the most important solution is to speak to your EDA vendor , I am sure all have solutions for you and some even give...
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4 years ago
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How to generate bits info for a record structure?
Hi, I have a data record designed as follows: type DATA_RECORD_t record I1: unsigned(7 downto 0); I2: unsigned(15 downto 0); end record; I want to get its bit number and don't want to manually...
9
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4 years ago
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9 | |
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Code block in icestudio
Hi, I'm trying to program a TinyFPGA BX to provide 3 registers to emulate an FDC9266, the bulk will later be done using an ATMega ucontroller. To sort out the A0,nCS,nRD,nWR,nDACK, I have inserted a...
16
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4 years ago
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how to suppress assertion warnings in gtkwave?
hello, is there any way to suppress assertion warnings from in gtkwave simulator? thank you
3
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4 years ago
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Apple eBook on Educational CPU design using FPGA
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4 years ago
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