Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Looking for a decent FPGA board with multiple Xilinx Virtex 5 FPGAs
Hi, I am looking for a decent PCIe (Gen1 & Gen2) based FPGA board with preferably 2 Xilinx Virtex 5 FPGAs on it. A 2GB DDR2 SODIMM and minimum 256 MB RAM is preferred. Other onboard periphals may...
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12 years ago
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Enterpoint New Boards
We have some new, and some not so new, offerings this week. The first out is a new member of the Merrick family. Merrick3 has 26 FPGAs and if that's not enough we can stack these boards. Details on...
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12 years ago
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Call for Papers (CFP)
========================================================= ARPN Journal of Science and Technology Call for Papers (Vol. 2 No. 1) January 2011 Dear Sir/ Madam, ARPN Journal of Science and Technology is...
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12 years ago
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ASIC design job vs FPGA design job
Hi folks, I am an ASIC design engineer with over 6 years experience. My experience in ASIC design spans across microarchitecture, RTL coding, synthesis, timing closure and verification. Is it...
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12 years ago
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Choose between Cyclone II and Spartan II
Hi All, I am starting a new project for a software defined radio using FPGA. I plan to use simulink and HDL coder with model based design. So far I have narrowed down the hardware to cyclone II EP2C70...
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12 years ago
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PCI Express development board
Hi, I'm looking for an FPGA-based PCI Express development board which is capable of transmitting data at about 1.4 GByte/sec to the host computer (PCIe Gen1 x8 or Gen2 x4/x8). Further considerations:...
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12 years ago
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Xilinx USB II Cable driver under Gentoo Linux
I'm looking for pointers to an installation guide on how to install the Xilinx USB II Cable driver under Gentoo Linux? I just took a quick look at the installation script(1) and found checks for...
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12 years ago
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draw lines, circles, squares on FPGA by mouse and display on VGA ( not use NIOS)
hi ! im from vietnam . my english is not good , i hope you can understand what i say . thanks ! i have project to graduate university . my project is draw circle , line , triagle in FPGA , display on...
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12 years ago
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[ANN] Free web access to the HercuLeS high-level synthesis tool
Dear all i'm pleased to announce that free access to the web interface of the HercuLeS high-level synthesis tool is now available. HercuLeS allows you to synthesize ANSI C code or generic-assembly...
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12 years ago
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Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
Co-sponsored by IEEE NCA Consultants Network, Baltimore Consultants Network, Society on Social Implications of Technology, Baltimore and NoVA/Wash. Computer Society, and Region 2 PACE Committee...
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12 years ago
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CSV pinout from Actel
Guys, Do you know if it is possible to get a complete pinout report from the Actel compilation flow? I want something complete like the CSV file that comes out of the Xilinx ISE compilation process. I...
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12 years ago
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Clock Phase Fun on Cyclone III
I've got a project going on a Cyclone III, and have hit an issue that seems like it has a simple solution if only I already knew it. I've got a 125 MHz input clock (CLK125). I've got an ADC that takes...
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12 years ago
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Modelsim on windoz save settings in a file rather than registry
Hi Is there any way of getting modelsim not to use the widoz registry for settings. I would prefer if it would use my .modelsim file. I find it impossible to express the extent of my disgust at having...
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12 years ago
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newable need help
hi all. im currently learning FPGAs and having big interesting in it. but the only place i can practice is the uni lab. i wanna practice at home with my own laptop as well. but i dont know which...
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12 years ago
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FPGA functional flow..please help!
Hallo, I am new in the world of FPGA. I am asked to design he functional flow for a image processing hardware. The hardware i.e FPGA will be used for video decompression . Hence it has to receive the...
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12 years ago
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