Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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MicroBlaze MCS Error.
Hi all. I'm T.Koyama. I download ISE 13.4 and make IP Microblze mcs. I could make IP and bitstream,and I make ELF file under SDK So I will download to FPGA, but Error ocuuer. Error meaaseg is...
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12 years ago
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clock enable question
I created the following clock enable block: library ieee; use use entity clock_enable is generic ( OUTPUT_CLOCK_ENABLE_PERIOD : time; INPUT_CLOCK_ENABLE_PERIOD : time ); port ( clk : in std_logic;...
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12 years ago
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What is value of scale_sch for FFT5.0 IP core for IFFT
We are using scaling in FFT5.0 IP Core for 64 transform size,radix 2 burst mode,natural order,scaling(so get same o/p size as i/p size), i/p data 8 bit and expected o/p data also 8 bit. For this we...
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12 years ago
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VCD to power consumption trace
Hi all, I have captured the toggle counts of my design in a VCD file and I wonder if there are now any tools available that allow me to plot a nice estimate of the dynamic power consumption of my...
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12 years ago
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ABEL to VHDL/Verilog converter
Hi, where i can get the tool to ocnvert ABEL HDL to VHDL/verilog converter. Thanks & Regards, sheik --------------------------------------- Posted through
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12 years ago
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Effective square root algorithms implemented on FPGAs already
Hello guys, I'm trying to find a little bit more information for efficient square root algorithms which are most likely implemented on FPGA. A lot of algorithms are found already but which one are for...
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12 years ago
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Virtex 5 GC clock pin vs GC//CC clock pins
Hi, What is the difference between a GC clock pin and a GC/CC clock pin(I dont mean a CC pin I mean a GC/CC pin)? Such as below for a V5 xc5vlx50t, package ff665,...
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12 years ago
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balancing IIR filter (after adding extra registers)
I designed a low pass IIR filter in starix iv but I got speed problem. I need to run it on 245MHz but can only achieve about 180. I was advised by experts to insert extra registers and this improved...
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12 years ago
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XLNX efuse anyone?
(repost from XLNX forum) Has anyone succesfully managed to program the eFuses? On the Virtex-6 in particular but any device would be good... There seems to be many restrictions and I am unclear if I...
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12 years ago
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opendous-jtag support for independent USB drivers for JTAG/Impact/Chipscope?
Hi, Probably most Linux users working with Xilinx tools use the excellent drivers written by Michael Gernoth and available at I'm looking for a way to embed the whole USBJTAG converter into device, so...
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12 years ago
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Xilinx SRAM clock-to-out and input constraint with forwarded clock
Hi, I have SRAM connected to a FPGA. The clock is forwarded to the SRAM by the FPGA (using ODDR trick). The input clock to the system is of another frequency and is internally multiplied by a DCM....
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12 years ago
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voltage drop on STRATIX FPGA supply planes
Guys I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power plane. It is showing a 30mV voltage drop across the BGA itself, let alone getting the power to the BGA which is dropping...
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12 years ago
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Handling overflow in a self-repeating frequency counter
Hi guys. I'm currently working on the HDL code for an open-source project which images 'strange and unusual' magnetic media (mainly floppy discs but also MFM and RLL hard disc drives). To do this, I...
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12 years ago
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Beginner question on FIFO in "FPGA prototyping by VHDL examples"
I am very new to FPGA programming. I'm using "FPGA Prototyping by VHDL examples" to learn VHDL. I've gotten up to section 4.5.3 FIFO buffer, and am having trouble understanding what might happen in...
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12 years ago
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Trying to select a development board, can somebody help me make an informed choice?
Hello, I am trying to decide what board to order for a project I want to do betwee= n April and June in school, and for other projects, mainly to exercise VHDL= and design interesting projects. The...
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12 years ago
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