Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Comparing relative power consumption
I am struggling to find a solution to my problem: I would like to get a (very) rough idea of the relative levels of power consumption used by equivelent devices from Altera's Cyclone III and IV ranges...
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12 years ago
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Back from Xilinx trainings
Hi: I spent the last two weeks at Xilinx in San Jose taking Doulos' "Comprehensive Verilog" and the "Essentials and Design for Performance" courses. Very enlightening. I was very impressed by the...
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12 years ago
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CPU Design in Xilinx Spartan 3E
Hello Every body, I have written a code in VHDL for 8 bit simple cpu and also have the test bench for this. The Opcodes are also written and implemented. I also have downloaded the bit files in...
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12 years ago
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Synchronizing Virtex-6 RocketIOs on RX path
Hi in a project I am using a Virtex-6 with GTX RocketIO transceivers which I want to interface with a 4x 6.5 Gb/s interface on the RX side. One project contraint is not to use any channel coding, i.e....
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12 years ago
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Virtex 6 System Monitor sensor readings in ChipScope gives weird values
Hi =20 We are doing initial testing of a new Virtex-6 based board that we develope= d. We are having problems when trying to access the system monitor informat= ion over JTAG. It is constantly showing...
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12 years ago
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FPGA Area
Hi all, I have question on measuring FPGA area. Measuring area cost of the FPGA implementation is tricky because there are several different area types LUT, FF, BRAM, DSP. Is there way look at a...
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12 years ago
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Error JTAG chain problem detected
My design worked for about 3 hours and now gives me this error. I just can't understand what is wrong with it now. I didn't do anything wrong. !Error: JTAG chain problem detected !Error: The TDI...
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12 years ago
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configuring an Altera Cyclone 3
Hi, I have an FPGA design that works from JTAG, and now I want to burn a serial flash chip so it will configure itself at powerup. The mode pins should be right for serial self-load, and we'll be...
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12 years ago
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Migrating Spartan2 design (xnf)
Because the Xilinx Spartan2 is going to be discontinued in the near future one of my customers asked me to migrate their designs to a newer Xilinx FPGA. Perhaps Spartan 6 or Artix 7. The problems are:...
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12 years ago
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JTAG to obsolete Lattice MACH131?
I've got a strange one. Someone's asked me to reprogram an old MACH131SP device, dating from about '95-98. Are any of you still doing this? Any advice? I don't yet know if they have sources...
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12 years ago
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Call for Papers Reminder: The 2012 International Conference of Electrical and Electronics Engineering (ICEEE 2012)
Call for Papers Reminder: The 2012 International Conference of Electrical and Electronics Engineering (ICEEE 2012) CFP Reminder: The 2012 International Conference of Electrical and Electronics...
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12 years ago
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Touchscreen For Terasic Technologies DE0 Nano
Hi, I am looking for a touchscreen for an DE0 Nano. Terasic's LTM touchscreen is supposed to work but the LTM manual does not mention it. Are there others? A seven inch screen is preferred. Thanks,...
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12 years ago
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"High Performance Computing in the Life/Medical Sciences" two week summer institute
Dear All, This is a national competition targeted to those interested in bio, HPC, FP= GAs, and tubing down the New River in the summer. Work will be performed o= n Convey HC-1 and HC-1ex FPGA-based...
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12 years ago
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Strassen algorithm in vhdl
hi all I am currently struggling trying to write Strassens Algorithm for matrix multiplication in VHDL. I have written the code for 2x2 matrices, but now have to develop it to implement 4x4 matrices...
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12 years ago
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What is a PLD/FPGA with serial or Ethernet port logic or block built in
I am looking for a chip with somekind of communication port inbuilt. I am slowly planning a system where some data is sent from a computer to be processed in the chip. Processing data is probably...
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12 years ago
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