Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Free Seminars/Labs - Implementing PCI Express Designs in FPGAs
Having not done any free seminars for a while we now fixing that by running 2 sets of seminars in May and possibly into June if we add some more dates. Both sets of seminars are based on the...
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11 years ago
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6 | |
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Very poor Xilinx experience
I'm hoping someone at Xilinx reads this, because I can't find any other way to get through to anyone to help me. Short version: I've bought an SP605 board, it looks as though it's broken - there's no...
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11 years ago
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10 | |
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Mandelbrot set on Spartan3
Hi, implemented the Mandelbrot set on Digilent's Starter Kit for Spartan 3. Is anyone interested in the .bit-file ? Regards Thorsten
5
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11 years ago
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Expectations from newly minted EE?
Fellas, I work in a historically software only industry, but have a project on my desk that would likely benefit from implementation on recent generation FPGA. My HDL skills are scant and ancient, and...
15
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11 years ago
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Re: Ball-park price of Xilinx Virtex 7 FPGA?
Search for XC7V on And better sit down before checking... Bye http://www.findchips.com.
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11 years ago
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17 | |
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Low latency FPGA options
Hello, I am looking to use FPGA's as specialized coprocessors to increase performance on different applications. I would like the lowest latency possible to memory. I have only found options with PCIE...
3
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11 years ago
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Could you explain these speed spec to me?
Hi, I get the following data from a on-line slide on MAP decoder. I think "Speed" is about the max clock rate. How about the "Fastest Implementation"? Could you explain it to me? Thanks. ...............
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11 years ago
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1 | |
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FPGA communication with a PC (Windows)
Hello all, My team needs to design our own piece of testing equipment for our project. I'll spare you the gory details, and just say that we will need to collect data at some 20 Mbyte/sec (possibly...
33
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12 years ago
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FPGA + Mess o' RAM
Does anyone have any experience connecting an FPGA to a serious mess of DRAM? I'm thinking of something on the order of 16GB, possibly just by buying/socketing 4x4GB standard DIMMs. I don't need...
3
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12 years ago
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3 | |
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Digital Tachometer VHDL
Many years ago (in the TTL days, likely before microprocessors) there was a digital tachometer design in an electronics magazine. To get a reasonable update rate, they used a PLL frequency multiplier....
6
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12 years ago
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Why are my S3A pins getting destroyed?
I have a S350A VQFP100 on my custom board, with all the pins connected to large pads all around the chip. I have destroyed 3 pins, total. Two pins can't be used as inputs anymore, and the third lost...
2
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12 years ago
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Spartan 3A counter speed ?
Hello, Does anybody have a very rough estimate of how fast you can run a 32-bit counter in a Spartan 3AN FPGA? Thanks, Jon
10
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12 years ago
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10 | |
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Virtex6HXT PCIe 8X Gen2 timing closure problem
I'm having a terrible time getting the V6 PCIe core to consistently meet timing, it works occasionally but usually it misses. I've used the suggested constraints that Coregen puts out but that doesn't...
1
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12 years ago
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1 | |
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Spartan 3 DiffPairs restricted to Banks 0 and 2?
On a PCI Card I got a XC3SD1800A-4FGG676C. While trying to establish a differential output pair on Pins K23,K22, i got the following message:...
2
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12 years ago
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2 | |
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Record type <-> std_logic_vector conversion - Python script
The record types in VHDL are very useful when designing more complicated systems. However if you need to store data of record types to memory or FIFO, it is necessary to convert such data to the...
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12 years ago
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