Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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DE10 Standard Audio Demos not working
Hello, I bought the DE10 Standard and am having issues trying to run the demos rel ated to audio. I am trying to run the two demos, DE10_Standard_Audio, and DE10_Standard_i2 sound, while connecting...
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3 years ago
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Active HDL and the Case of the Haunted Cursor
Active HDL is really starting to piss me off. I can't understand some of t he things it does. Now the cursor won't stay where I put it. It keeps mov ing to the end of the simulation a few seconds...
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3 years ago
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Go To VHDL Resource
I started a new design the other day and realized I had forgotten which web sites were good VHDL resources. There are resources for the language, there are good resources for the many libraries and...
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3 years ago
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Bit Swizzling
I'm not sure where to ask this question, so I pushed it out to several groups. You need not reply to all of them if you don't think it is a topical subject. I included in a previous message, but it...
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3 years ago
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What is a Processor and Software in Context of Reliability Analysis?
How is a "processor" defined when considering requirements on developing a design? A project I am on is shoving software into HDL to design an FPGA w hich is being considered "hardware". I'm not...
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3 years ago
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ADCs in FPGAs
I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it. Lattice has a...
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3 years ago
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Are Gowin Serious Contenders?
I'm looking at using Gowin in a design and I not sure about them. They are being sold at Mouser, but the prices are not so great. Their cheapest 1 k LUT chips are not too bad at $3@1k, but from there...
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3 years ago
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iCE40 Ultra Family Data Sheet
Looking at section 4.5 the power up supply sequence is clearly stated to st art with Vcc/Vccpll, then to bring up SPI_VCCIO1 followed by VPP_2V5 with t he remaining supplies to be brought up anytime...
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3 years ago
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Potential New Design
I might be working on a smallish design shortly and I'm picking an FPGA. I don't have much in the way of requirments yet, but I'd like to have at lea st 2000 LUTs, 39 I/Os or more, but most...
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3 years ago
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Elastic buffer implementation
For this article : Implementing Latency-Insensitive Dataflow Blocks at http :// 1) How is "Hold" action different from "Buffer" action ? 2) Why is the '1' pin of the second multiplexer inside the...
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3 years ago
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Some preliminary help for an FPGA selection
It will be the first FPGA for me. What I want to do is not complex, I have done similar controllers (more complex really)numerous times using logic parts, PLD, CPLD-s etc. I need to put together a...
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3 years ago
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Entity-bound SDC file in Quartus Lite Edition?
Hi, I need to port my design from Xilinx FPGA based board to a Altera/Intel FPGA based one. The design must be available for students, who need to use the Quartus Lite Edition. One of essential things...
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3 years ago
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ICCD 2020: Call for Special Sessions and Tutorial Proposals
========================= ========================= ========= ICCD 2020: Call for Special Sessions and Tutorial Proposals ========================= ========================= ========= The...
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3 years ago
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Lattice new 28nm series - any clues about availability ?
Just a few days ago, they presented Certus-NX series that is based on their new Nexus platform. Has anyone here been testing these and what else can we expect on 28nm ? Will there be ECP3 and XO3...
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3 years ago
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<whine mode on> Why is my source buried in the bowels of the project?
I've always found it awkward that when I create a project the various tempo rary files the tool creates are at the top of the project tree and my files are down at the end of a branch of the...
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3 years ago
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