Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
TCE 1.6
TTA-based Co-design Environment (TCE) v1.6 released --------------------------------------------------- TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors...
 
MPMC does not finish initialization in simulation
Hello Friends, I am working on virtex6. I am trying to debug a problem by simulating in modelsim. But in the simulation I get a different problem. My platform uses DDR3 SDRAM via xilinx's MPMC...
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Questions about LCMXO2280-B-EVN and LCMXO2-1200ZE-B-EVN ev kits
There are too many FPGAa and CPLDs. I can see that LCMXO2280-B-EVN has 8 40-pin connectors, which is important to me. But what else is there and what I am missing. And then there is Xilinx too. By the...
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PRNG
I need a multi-bit PRNG which generates a sequence of 10-bit pseudo random numbers. Can I use a LFSR of sufficient length (31 bit, for example), and get a new random number on each clock by using the...
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Variables, signals: behavioral and post-route simulation
I'm learning the diff between variables and signals, and I've found this site: a corresponding picture here: I've changed the source file to this library ieee; use entity sig_var is port ( d1, d2, d3...
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ISERDES2 divide factor
Hi all, I have a Spartan-6 LX45 board with a whole bunch of lvds going in and out at a rate of 780mbps. After running out of pins I was forced to put two lvds receiving pairs into a different bank...
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EDK problems
Does anyone have experience of using the Altera and Xilinx embedded software? I have been using EDK but I am getting very frustrated with it. It seems that every new release includes a generous...
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Read output from external chip using microblaze
Hi all I got stuck with my design. I'm planning to use microblaze in ML505 board to read my full custom chip output and display to hyperterminal. I've found one tutorial about read DIP switch using...
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Logic Glitches in Spartan-3?
I've got a 24-input AND gate that I'd like to avoid having add another register delay to before I toss it across a clock boundary. all_done
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Announcement: Sigasi integrates with Aldec compiler
Dear hardware designers, In its latest release, Sigasi Pro 2.4 integrates with the Aldec Riviera-PRO simulator to accelerate the design feedback cycle. Check out this three minute video on how to find...
 
ITU656 to Mpeg4 with Fpga?
An ADV7181BBSTZ - PAL/NTSC Video Decoder coverts an analogue video camera signal to ITU656 and YCrCb 4:2:2 [ Serial digital stream]. Convert this to JPEG over Ethernet with a FpGa as implemented by...
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Xilinx ISE Multiple Drivers Error
Hi folks, I seem to have convinced ISE to output incorrect multiple-driver error messages. I've reduced the example to the following: -- test.vhd library ieee; use entity Test is port( Clock : in...
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banks and its association with options
oops, After discussing about the banks, it is certainly appropriate to take into account the monitoring of the options wisely; could you explain how to extend banks data management? Yours, sincerely
 
Spartan-6 66mhz pci
I'm trying to make a simple PCI interface in a XC6SLX45. In the end I'll probably go with the premade Xilinx core but I wanted to get familiar with the details first. It seems that the chip simply...
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Synthesis Problem
I have this code written in verilog for a counter but my program xilinx ise 14.1 finds 2 errors: ERROR:Xst:899 - "numarator9.v" line 45: The logic for does not match a known FF or Latch template. The...
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