Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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A total beginner, wondering about determining hardware specs. requirements
Hi, I'm just starting to learn Verilog/systemverilog and I've been running some of my code through simulators to ensure that it works, but I am looking into acquiring a development board for further...
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11 years ago
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question about verilog ?, :
Hi, I know some VHDL, but totally new to verilog. Now I am reading a verilog template. I do not know the meaning of the following code: assign ce_hciccomp_decode = (cur_count == 0 && clk_enable ==...
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11 years ago
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Question about TCL command of modelsim
Hi, I do not understand the .tcl command, which is issued by Matlab Simulink to run Modelsim in HDL Coder. More specifically, I do not understand the 'after' command below. After I search some...
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11 years ago
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viewing old aldec/xilinx foundation schematics
Hi, we have a very old project where schematic entry was used using the xil inx foundation 3 software with aldec schematics. New xilinx systems are not able to read these schematics. Is anybody around...
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11 years ago
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ST Micro GOSPL open source EDA tools?
Hi, around 2004, there was an effort by ST Micro to enter the FPGA market. In t his context, ST published a set of open source EDA tools named "GOSPL" on h ttp:// - the tools were mentioned, e.g., in...
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11 years ago
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What the advantages and disadvantages between distributed arithmetic and seial-parallel based MAC?
Hi, For a filter implementation in FPGA/ASIC, there are two efficient architect ures for the MAC. One is distributed arithmetic, while the other is serial- parallel multiplication based. I know that...
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11 years ago
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pci express reference clock step down
A PCI Express master (a "root complex") generates a 100 MHz reference clock to target devices. In some cases that we've observed, the master (in this case, an AMI based motherboard) ramps the clock...
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11 years ago
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Is it possible to use MachXO2 Demo board to program an external FPGA?
I use the MachXO2?-1200ZE Breakout Board. I noticed that independent programmers for the FPGA (LCMXO2-1200ZE) are expensive. Is it possible to bridge wires from the Demo board to an external board to...
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11 years ago
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Real Time Protocol - RTP using FPGA
in my pc there is a DB with songs and i want to send/ transmit using RTP real time protocol to different devices so I want send media over RTP/UDP/IP using fpgas
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11 years ago
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Xilinx XC3S400 reproducibility madness
Hello all I am facing a strange problem: I am not able to generate a properly working bitstream from an original set of files that worked perfectly well just a few days ago. I mean, the FPGA gets...
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11 years ago
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Lowest Power Design in an FPGA
What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that push...
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11 years ago
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Altera FPGA: EP4CE10 as drop-in replacement for EP4CE15 (F17)
Hi. I want to verify if it is possible to use the CE10 to replace the CE15. Som e pins that are GND or VCCIO/VCCINT/VCCA on the CE15 are IOs on the CE10. T he GNDs are not a problem. But pins...
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11 years ago
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TMDS CML PCB
Hello, I have problem with understanding differential nature of DC coupled CML pair in TDMS (DVI, HDMI). In DC coupled LVDS current flows from source through one wire of transmission line then through...
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11 years ago
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Using LVDS Input for Delta Sigma ADC
I found an app note on the Lattice site about using the LVDS input as the input comparator. My design is very low power and I am concerned about the power consumption of this input. Typically inputs...
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11 years ago
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RTL simulation of Dynamic Partial Reconfiguration and Dynamically Reconfigurable FPGA designs
Hi, Are you working on Dynamic Partial Reconfiguration (DPR)? Are you strugglin g to get your DPR design working? Are you frustrated with using ChipScope? I am a PhD student from the University of New...
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11 years ago
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